1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2016 Marvell International Ltd. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun * https://spdx.org/licenses 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include <asm/arch-armada8k/cache_llc.h> 9*4882a593Smuzhiyun#include <linux/linkage.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/* 12*4882a593Smuzhiyun * int __asm_flush_l3_dcache 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * flush Armada-8K last level cache. 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun */ 17*4882a593SmuzhiyunENTRY(__asm_flush_l3_dcache) 18*4882a593Smuzhiyun /* flush cache */ 19*4882a593Smuzhiyun mov x0, #LLC_BASE_ADDR 20*4882a593Smuzhiyun add x0, x0, #LLC_FLUSH_BY_WAY 21*4882a593Smuzhiyun movk x0, #MVEBU_A8K_REGS_BASE_MSB, lsl #16 22*4882a593Smuzhiyun mov w1, #LLC_WAY_MASK 23*4882a593Smuzhiyun str w1, [x0] 24*4882a593Smuzhiyun /* sync cache */ 25*4882a593Smuzhiyun mov x0, #LLC_BASE_ADDR 26*4882a593Smuzhiyun add x0, x0, #LLC_CACHE_SYNC 27*4882a593Smuzhiyun movk x0, #MVEBU_A8K_REGS_BASE_MSB, lsl #16 28*4882a593Smuzhiyun str wzr, [x0] 29*4882a593Smuzhiyun /* check that cache sync completed */ 30*4882a593Smuzhiyun mov x0, #LLC_BASE_ADDR 31*4882a593Smuzhiyun add x0, x0, #LLC_CACHE_SYNC_COMPLETE 32*4882a593Smuzhiyun movk x0, #MVEBU_A8K_REGS_BASE_MSB, lsl #16 33*4882a593Smuzhiyun1: ldr w1, [x0] 34*4882a593Smuzhiyun and w1, w1, #LLC_CACHE_SYNC_MASK 35*4882a593Smuzhiyun cbnz w1, 1b 36*4882a593Smuzhiyun /* return success */ 37*4882a593Smuzhiyun mov x0, #0 38*4882a593Smuzhiyun ret 39*4882a593SmuzhiyunENDPROC(__asm_flush_l3_dcache) 40