1 /*
2 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <common.h>
8 #include <dm.h>
9 #include <fdtdec.h>
10 #include <linux/libfdt.h>
11 #include <asm/io.h>
12 #include <asm/system.h>
13 #include <asm/arch/cpu.h>
14 #include <asm/arch/soc.h>
15 #include <asm/armv8/mmu.h>
16
17 DECLARE_GLOBAL_DATA_PTR;
18
19 /* Armada 3700 */
20 #define MVEBU_GPIO_NB_REG_BASE (MVEBU_REGISTER(0x13800))
21
22 #define MVEBU_TEST_PIN_LATCH_N (MVEBU_GPIO_NB_REG_BASE + 0x8)
23 #define MVEBU_XTAL_MODE_MASK BIT(9)
24 #define MVEBU_XTAL_MODE_OFFS 9
25 #define MVEBU_XTAL_CLOCK_25MHZ 0x0
26 #define MVEBU_XTAL_CLOCK_40MHZ 0x1
27
28 #define MVEBU_NB_WARM_RST_REG (MVEBU_GPIO_NB_REG_BASE + 0x40)
29 #define MVEBU_NB_WARM_RST_MAGIC_NUM 0x1d1e
30
31 static struct mm_region mvebu_mem_map[] = {
32 {
33 /* RAM */
34 .phys = 0x0UL,
35 .virt = 0x0UL,
36 .size = 0x80000000UL,
37 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
38 PTE_BLOCK_INNER_SHARE
39 },
40 {
41 /* SRAM, MMIO regions */
42 .phys = 0xd0000000UL,
43 .virt = 0xd0000000UL,
44 .size = 0x02000000UL, /* 32MiB internal registers */
45 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
46 PTE_BLOCK_NON_SHARE
47 },
48 {
49 /* List terminator */
50 0,
51 }
52 };
53
54 struct mm_region *mem_map = mvebu_mem_map;
55
reset_cpu(ulong ignored)56 void reset_cpu(ulong ignored)
57 {
58 /*
59 * Write magic number of 0x1d1e to North Bridge Warm Reset register
60 * to trigger warm reset
61 */
62 writel(MVEBU_NB_WARM_RST_MAGIC_NUM, MVEBU_NB_WARM_RST_REG);
63 }
64
65 /*
66 * get_ref_clk
67 *
68 * return: reference clock in MHz (25 or 40)
69 */
get_ref_clk(void)70 u32 get_ref_clk(void)
71 {
72 u32 regval;
73
74 regval = (readl(MVEBU_TEST_PIN_LATCH_N) & MVEBU_XTAL_MODE_MASK) >>
75 MVEBU_XTAL_MODE_OFFS;
76
77 if (regval == MVEBU_XTAL_CLOCK_25MHZ)
78 return 25;
79 else
80 return 40;
81 }
82