1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2016 Stefan Roese <sr@denx.de>
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <dm.h>
9*4882a593Smuzhiyun #include <fdtdec.h>
10*4882a593Smuzhiyun #include <linux/libfdt.h>
11*4882a593Smuzhiyun #include <asm/io.h>
12*4882a593Smuzhiyun #include <asm/system.h>
13*4882a593Smuzhiyun #include <asm/arch/cpu.h>
14*4882a593Smuzhiyun #include <asm/arch/soc.h>
15*4882a593Smuzhiyun #include <asm/armv8/mmu.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /* Armada 3700 */
20*4882a593Smuzhiyun #define MVEBU_GPIO_NB_REG_BASE (MVEBU_REGISTER(0x13800))
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #define MVEBU_TEST_PIN_LATCH_N (MVEBU_GPIO_NB_REG_BASE + 0x8)
23*4882a593Smuzhiyun #define MVEBU_XTAL_MODE_MASK BIT(9)
24*4882a593Smuzhiyun #define MVEBU_XTAL_MODE_OFFS 9
25*4882a593Smuzhiyun #define MVEBU_XTAL_CLOCK_25MHZ 0x0
26*4882a593Smuzhiyun #define MVEBU_XTAL_CLOCK_40MHZ 0x1
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define MVEBU_NB_WARM_RST_REG (MVEBU_GPIO_NB_REG_BASE + 0x40)
29*4882a593Smuzhiyun #define MVEBU_NB_WARM_RST_MAGIC_NUM 0x1d1e
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun static struct mm_region mvebu_mem_map[] = {
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun /* RAM */
34*4882a593Smuzhiyun .phys = 0x0UL,
35*4882a593Smuzhiyun .virt = 0x0UL,
36*4882a593Smuzhiyun .size = 0x80000000UL,
37*4882a593Smuzhiyun .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
38*4882a593Smuzhiyun PTE_BLOCK_INNER_SHARE
39*4882a593Smuzhiyun },
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun /* SRAM, MMIO regions */
42*4882a593Smuzhiyun .phys = 0xd0000000UL,
43*4882a593Smuzhiyun .virt = 0xd0000000UL,
44*4882a593Smuzhiyun .size = 0x02000000UL, /* 32MiB internal registers */
45*4882a593Smuzhiyun .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
46*4882a593Smuzhiyun PTE_BLOCK_NON_SHARE
47*4882a593Smuzhiyun },
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun /* List terminator */
50*4882a593Smuzhiyun 0,
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun struct mm_region *mem_map = mvebu_mem_map;
55*4882a593Smuzhiyun
reset_cpu(ulong ignored)56*4882a593Smuzhiyun void reset_cpu(ulong ignored)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun /*
59*4882a593Smuzhiyun * Write magic number of 0x1d1e to North Bridge Warm Reset register
60*4882a593Smuzhiyun * to trigger warm reset
61*4882a593Smuzhiyun */
62*4882a593Smuzhiyun writel(MVEBU_NB_WARM_RST_MAGIC_NUM, MVEBU_NB_WARM_RST_REG);
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /*
66*4882a593Smuzhiyun * get_ref_clk
67*4882a593Smuzhiyun *
68*4882a593Smuzhiyun * return: reference clock in MHz (25 or 40)
69*4882a593Smuzhiyun */
get_ref_clk(void)70*4882a593Smuzhiyun u32 get_ref_clk(void)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun u32 regval;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun regval = (readl(MVEBU_TEST_PIN_LATCH_N) & MVEBU_XTAL_MODE_MASK) >>
75*4882a593Smuzhiyun MVEBU_XTAL_MODE_OFFS;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun if (regval == MVEBU_XTAL_CLOCK_25MHZ)
78*4882a593Smuzhiyun return 25;
79*4882a593Smuzhiyun else
80*4882a593Smuzhiyun return 40;
81*4882a593Smuzhiyun }
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