1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2016 Stefan Roese <sr@denx.de> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <common.h> 8*4882a593Smuzhiyun #include <dm.h> 9*4882a593Smuzhiyun #include <fdtdec.h> 10*4882a593Smuzhiyun #include <linux/libfdt.h> 11*4882a593Smuzhiyun #include <pci.h> 12*4882a593Smuzhiyun #include <asm/io.h> 13*4882a593Smuzhiyun #include <asm/system.h> 14*4882a593Smuzhiyun #include <asm/arch/cpu.h> 15*4882a593Smuzhiyun #include <asm/arch/soc.h> 16*4882a593Smuzhiyun #include <asm/armv8/mmu.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* 21*4882a593Smuzhiyun * Not all memory is mapped in the MMU. So we need to restrict the 22*4882a593Smuzhiyun * memory size so that U-Boot does not try to access it. Also, the 23*4882a593Smuzhiyun * internal registers are located at 0xf000.0000 - 0xffff.ffff. 24*4882a593Smuzhiyun * Currently only 2GiB are mapped for system memory. This is what 25*4882a593Smuzhiyun * we pass to the U-Boot subsystem here. 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun #define USABLE_RAM_SIZE 0x80000000 28*4882a593Smuzhiyun board_get_usable_ram_top(ulong total_size)29*4882a593Smuzhiyunulong board_get_usable_ram_top(ulong total_size) 30*4882a593Smuzhiyun { 31*4882a593Smuzhiyun if (gd->ram_size > USABLE_RAM_SIZE) 32*4882a593Smuzhiyun return USABLE_RAM_SIZE; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun return gd->ram_size; 35*4882a593Smuzhiyun } 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* 38*4882a593Smuzhiyun * On ARMv8, MBus is not configured in U-Boot. To enable compilation 39*4882a593Smuzhiyun * of the already implemented drivers, lets add a dummy version of 40*4882a593Smuzhiyun * this function so that linking does not fail. 41*4882a593Smuzhiyun */ mvebu_mbus_dram_info(void)42*4882a593Smuzhiyunconst struct mbus_dram_target_info *mvebu_mbus_dram_info(void) 43*4882a593Smuzhiyun { 44*4882a593Smuzhiyun return NULL; 45*4882a593Smuzhiyun } 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* DRAM init code ... */ 48*4882a593Smuzhiyun dram_init_banksize(void)49*4882a593Smuzhiyunint dram_init_banksize(void) 50*4882a593Smuzhiyun { 51*4882a593Smuzhiyun fdtdec_setup_memory_banksize(); 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun return 0; 54*4882a593Smuzhiyun } 55*4882a593Smuzhiyun dram_init(void)56*4882a593Smuzhiyunint dram_init(void) 57*4882a593Smuzhiyun { 58*4882a593Smuzhiyun if (fdtdec_setup_memory_size() != 0) 59*4882a593Smuzhiyun return -EINVAL; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun return 0; 62*4882a593Smuzhiyun } 63*4882a593Smuzhiyun arch_cpu_init(void)64*4882a593Smuzhiyunint arch_cpu_init(void) 65*4882a593Smuzhiyun { 66*4882a593Smuzhiyun /* Nothing to do (yet) */ 67*4882a593Smuzhiyun return 0; 68*4882a593Smuzhiyun } 69*4882a593Smuzhiyun arch_early_init_r(void)70*4882a593Smuzhiyunint arch_early_init_r(void) 71*4882a593Smuzhiyun { 72*4882a593Smuzhiyun struct udevice *dev; 73*4882a593Smuzhiyun int ret; 74*4882a593Smuzhiyun int i; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* 77*4882a593Smuzhiyun * Loop over all MISC uclass drivers to call the comphy code 78*4882a593Smuzhiyun * and init all CP110 devices enabled in the DT 79*4882a593Smuzhiyun */ 80*4882a593Smuzhiyun i = 0; 81*4882a593Smuzhiyun while (1) { 82*4882a593Smuzhiyun /* Call the comphy code via the MISC uclass driver */ 83*4882a593Smuzhiyun ret = uclass_get_device(UCLASS_MISC, i++, &dev); 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* We're done, once no further CP110 device is found */ 86*4882a593Smuzhiyun if (ret) 87*4882a593Smuzhiyun break; 88*4882a593Smuzhiyun } 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* Cause the SATA device to do its early init */ 91*4882a593Smuzhiyun uclass_first_device(UCLASS_AHCI, &dev); 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #ifdef CONFIG_DM_PCI 94*4882a593Smuzhiyun /* Trigger PCIe devices detection */ 95*4882a593Smuzhiyun pci_init(); 96*4882a593Smuzhiyun #endif 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun return 0; 99*4882a593Smuzhiyun } 100