1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * linux/arch/arm/mach-kirkwood/mpp.h -- Multi Purpose Pins 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright 2009: Marvell Technology Group Ltd. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __KIRKWOOD_MPP_H 10*4882a593Smuzhiyun #define __KIRKWOOD_MPP_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281) ( \ 13*4882a593Smuzhiyun /* MPP number */ ((_num) & 0xff) | \ 14*4882a593Smuzhiyun /* MPP select value */ (((_sel) & 0xf) << 8) | \ 15*4882a593Smuzhiyun /* may be input signal */ ((!!(_in)) << 12) | \ 16*4882a593Smuzhiyun /* may be output signal */ ((!!(_out)) << 13) | \ 17*4882a593Smuzhiyun /* available on F6180 */ ((!!(_F6180)) << 14) | \ 18*4882a593Smuzhiyun /* available on F6190 */ ((!!(_F6190)) << 15) | \ 19*4882a593Smuzhiyun /* available on F6192 */ ((!!(_F6192)) << 16) | \ 20*4882a593Smuzhiyun /* available on F6281 */ ((!!(_F6281)) << 17)) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define MPP_NUM(x) ((x) & 0xff) 23*4882a593Smuzhiyun #define MPP_SEL(x) (((x) >> 8) & 0xf) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* num sel i o 6180 6190 6192 6281 */ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0, 0, 0 ) 28*4882a593Smuzhiyun #define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0, 0, 0 ) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0 ) 31*4882a593Smuzhiyun #define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0 ) 32*4882a593Smuzhiyun #define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0 ) 33*4882a593Smuzhiyun #define MPP_F6281_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 1 ) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1 ) 36*4882a593Smuzhiyun #define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1 ) 37*4882a593Smuzhiyun #define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1 ) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1 ) 40*4882a593Smuzhiyun #define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1 ) 41*4882a593Smuzhiyun #define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1 ) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1 ) 44*4882a593Smuzhiyun #define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1 ) 45*4882a593Smuzhiyun #define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1 ) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1 ) 48*4882a593Smuzhiyun #define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1 ) 49*4882a593Smuzhiyun #define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1 ) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1 ) 52*4882a593Smuzhiyun #define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1 ) 53*4882a593Smuzhiyun #define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1 ) 54*4882a593Smuzhiyun #define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1 ) 55*4882a593Smuzhiyun #define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1 ) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1 ) 58*4882a593Smuzhiyun #define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1 ) 59*4882a593Smuzhiyun #define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1 ) 60*4882a593Smuzhiyun #define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1 ) 61*4882a593Smuzhiyun #define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1 ) 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1 ) 64*4882a593Smuzhiyun #define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1 ) 65*4882a593Smuzhiyun #define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1 ) 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1 ) 68*4882a593Smuzhiyun #define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1 ) 69*4882a593Smuzhiyun #define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1 ) 70*4882a593Smuzhiyun #define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1 ) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1 ) 73*4882a593Smuzhiyun #define MPP8_TW_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1 ) 74*4882a593Smuzhiyun #define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1 ) 75*4882a593Smuzhiyun #define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1 ) 76*4882a593Smuzhiyun #define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1 ) 77*4882a593Smuzhiyun #define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1 ) 78*4882a593Smuzhiyun #define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1 ) 79*4882a593Smuzhiyun #define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1 ) 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1 ) 82*4882a593Smuzhiyun #define MPP9_TW_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1 ) 83*4882a593Smuzhiyun #define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1 ) 84*4882a593Smuzhiyun #define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1 ) 85*4882a593Smuzhiyun #define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1 ) 86*4882a593Smuzhiyun #define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1 ) 87*4882a593Smuzhiyun #define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1 ) 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1 ) 90*4882a593Smuzhiyun #define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1 ) 91*4882a593Smuzhiyun #define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1 ) 92*4882a593Smuzhiyun #define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1 ) 93*4882a593Smuzhiyun #define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1 ) 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1 ) 96*4882a593Smuzhiyun #define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1 ) 97*4882a593Smuzhiyun #define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1 ) 98*4882a593Smuzhiyun #define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1 ) 99*4882a593Smuzhiyun #define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1 ) 100*4882a593Smuzhiyun #define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1 ) 101*4882a593Smuzhiyun #define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1 ) 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1 ) 104*4882a593Smuzhiyun #define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1 ) 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1 ) 107*4882a593Smuzhiyun #define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1 ) 108*4882a593Smuzhiyun #define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1 ) 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun #define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1 ) 111*4882a593Smuzhiyun #define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1 ) 112*4882a593Smuzhiyun #define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1 ) 113*4882a593Smuzhiyun #define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1 ) 114*4882a593Smuzhiyun #define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1 ) 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun #define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1 ) 117*4882a593Smuzhiyun #define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1 ) 118*4882a593Smuzhiyun #define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1 ) 119*4882a593Smuzhiyun #define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1 ) 120*4882a593Smuzhiyun #define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1 ) 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun #define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1 ) 123*4882a593Smuzhiyun #define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1 ) 124*4882a593Smuzhiyun #define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1 ) 125*4882a593Smuzhiyun #define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1 ) 126*4882a593Smuzhiyun #define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1 ) 127*4882a593Smuzhiyun #define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1 ) 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun #define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1 ) 130*4882a593Smuzhiyun #define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1 ) 131*4882a593Smuzhiyun #define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1 ) 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun #define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1 ) 134*4882a593Smuzhiyun #define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1 ) 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun #define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1 ) 137*4882a593Smuzhiyun #define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1 ) 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun #define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1 ) 140*4882a593Smuzhiyun #define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1 ) 141*4882a593Smuzhiyun #define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1 ) 142*4882a593Smuzhiyun #define MPP20_GE1_0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1 ) 143*4882a593Smuzhiyun #define MPP20_AUDIO_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1 ) 144*4882a593Smuzhiyun #define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1 ) 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1 ) 147*4882a593Smuzhiyun #define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1 ) 148*4882a593Smuzhiyun #define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1 ) 149*4882a593Smuzhiyun #define MPP21_GE1_1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1 ) 150*4882a593Smuzhiyun #define MPP21_AUDIO_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1 ) 151*4882a593Smuzhiyun #define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1 ) 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun #define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1 ) 154*4882a593Smuzhiyun #define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1 ) 155*4882a593Smuzhiyun #define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1 ) 156*4882a593Smuzhiyun #define MPP22_GE1_2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1 ) 157*4882a593Smuzhiyun #define MPP22_AUDIO_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1 ) 158*4882a593Smuzhiyun #define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1 ) 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun #define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1 ) 161*4882a593Smuzhiyun #define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1 ) 162*4882a593Smuzhiyun #define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1 ) 163*4882a593Smuzhiyun #define MPP23_GE1_3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1 ) 164*4882a593Smuzhiyun #define MPP23_AUDIO_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1 ) 165*4882a593Smuzhiyun #define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1 ) 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun #define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1 ) 168*4882a593Smuzhiyun #define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1 ) 169*4882a593Smuzhiyun #define MPP24_TDM_SPI_CS0 DEV( 24, 0x2, 0, 1, 0, 0, 1, 1 ) 170*4882a593Smuzhiyun #define MPP24_GE1_4 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1 ) 171*4882a593Smuzhiyun #define MPP24_AUDIO_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1 ) 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun #define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1 ) 174*4882a593Smuzhiyun #define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1 ) 175*4882a593Smuzhiyun #define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1 ) 176*4882a593Smuzhiyun #define MPP25_GE1_5 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1 ) 177*4882a593Smuzhiyun #define MPP25_AUDIO_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1 ) 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun #define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1 ) 180*4882a593Smuzhiyun #define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1 ) 181*4882a593Smuzhiyun #define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1 ) 182*4882a593Smuzhiyun #define MPP26_GE1_6 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1 ) 183*4882a593Smuzhiyun #define MPP26_AUDIO_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1 ) 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun #define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1 ) 186*4882a593Smuzhiyun #define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1 ) 187*4882a593Smuzhiyun #define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1 ) 188*4882a593Smuzhiyun #define MPP27_GE1_7 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1 ) 189*4882a593Smuzhiyun #define MPP27_AUDIO_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1 ) 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun #define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1 ) 192*4882a593Smuzhiyun #define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1 ) 193*4882a593Smuzhiyun #define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1 ) 194*4882a593Smuzhiyun #define MPP28_GE1_8 MPP( 28, 0x3, 0, 0, 0, 1, 1, 1 ) 195*4882a593Smuzhiyun #define MPP28_AUDIO_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1 ) 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun #define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1 ) 198*4882a593Smuzhiyun #define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1 ) 199*4882a593Smuzhiyun #define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1 ) 200*4882a593Smuzhiyun #define MPP29_GE1_9 MPP( 29, 0x3, 0, 0, 0, 1, 1, 1 ) 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun #define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1 ) 203*4882a593Smuzhiyun #define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1 ) 204*4882a593Smuzhiyun #define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1 ) 205*4882a593Smuzhiyun #define MPP30_GE1_10 MPP( 30, 0x3, 0, 0, 0, 1, 1, 1 ) 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun #define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1 ) 208*4882a593Smuzhiyun #define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1 ) 209*4882a593Smuzhiyun #define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1 ) 210*4882a593Smuzhiyun #define MPP31_GE1_11 MPP( 31, 0x3, 0, 0, 0, 1, 1, 1 ) 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun #define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1 ) 213*4882a593Smuzhiyun #define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1 ) 214*4882a593Smuzhiyun #define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1 ) 215*4882a593Smuzhiyun #define MPP32_GE1_12 MPP( 32, 0x3, 0, 0, 0, 1, 1, 1 ) 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun #define MPP33_GPIO MPP( 33, 0x0, 1, 1, 0, 1, 1, 1 ) 218*4882a593Smuzhiyun #define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1 ) 219*4882a593Smuzhiyun #define MPP33_GE1_13 MPP( 33, 0x3, 0, 0, 0, 1, 1, 1 ) 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun #define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1 ) 222*4882a593Smuzhiyun #define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1 ) 223*4882a593Smuzhiyun #define MPP34_GE1_14 MPP( 34, 0x3, 0, 0, 0, 1, 1, 1 ) 224*4882a593Smuzhiyun 225*4882a593Smuzhiyun #define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1 ) 226*4882a593Smuzhiyun #define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1 ) 227*4882a593Smuzhiyun #define MPP35_GE1_15 MPP( 35, 0x3, 0, 0, 0, 1, 1, 1 ) 228*4882a593Smuzhiyun #define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1 ) 229*4882a593Smuzhiyun #define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1 ) 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun #define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1 ) 232*4882a593Smuzhiyun #define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1 ) 233*4882a593Smuzhiyun #define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1 ) 234*4882a593Smuzhiyun #define MPP36_AUDIO_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1 ) 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun #define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1 ) 237*4882a593Smuzhiyun #define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1 ) 238*4882a593Smuzhiyun #define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1 ) 239*4882a593Smuzhiyun #define MPP37_AUDIO_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1 ) 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun #define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1 ) 242*4882a593Smuzhiyun #define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1 ) 243*4882a593Smuzhiyun #define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1 ) 244*4882a593Smuzhiyun #define MPP38_AUDIO_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1 ) 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun #define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1 ) 247*4882a593Smuzhiyun #define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1 ) 248*4882a593Smuzhiyun #define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1 ) 249*4882a593Smuzhiyun #define MPP39_AUDIO_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1 ) 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun #define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1 ) 252*4882a593Smuzhiyun #define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1 ) 253*4882a593Smuzhiyun #define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1 ) 254*4882a593Smuzhiyun #define MPP40_AUDIO_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1 ) 255*4882a593Smuzhiyun 256*4882a593Smuzhiyun #define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1 ) 257*4882a593Smuzhiyun #define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1 ) 258*4882a593Smuzhiyun #define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1 ) 259*4882a593Smuzhiyun #define MPP41_AUDIO_I2SLRC MPP( 41, 0x4, 0, 1, 1, 0, 0, 1 ) 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun #define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1 ) 262*4882a593Smuzhiyun #define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1 ) 263*4882a593Smuzhiyun #define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1 ) 264*4882a593Smuzhiyun #define MPP42_AUDIO_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1 ) 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun #define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1 ) 267*4882a593Smuzhiyun #define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1 ) 268*4882a593Smuzhiyun #define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1 ) 269*4882a593Smuzhiyun #define MPP43_AUDIO_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1 ) 270*4882a593Smuzhiyun 271*4882a593Smuzhiyun #define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1 ) 272*4882a593Smuzhiyun #define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1 ) 273*4882a593Smuzhiyun #define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1 ) 274*4882a593Smuzhiyun #define MPP44_AUDIO_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1 ) 275*4882a593Smuzhiyun 276*4882a593Smuzhiyun #define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1 ) 277*4882a593Smuzhiyun #define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1 ) 278*4882a593Smuzhiyun #define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1 ) 279*4882a593Smuzhiyun 280*4882a593Smuzhiyun #define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1 ) 281*4882a593Smuzhiyun #define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1 ) 282*4882a593Smuzhiyun #define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1 ) 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun #define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1 ) 285*4882a593Smuzhiyun #define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1 ) 286*4882a593Smuzhiyun #define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1 ) 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun #define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1 ) 289*4882a593Smuzhiyun #define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1 ) 290*4882a593Smuzhiyun #define MPP48_TDM_DTX MPP( 48, 0x2, 0, 1, 0, 0, 0, 1 ) 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun #define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1 ) 293*4882a593Smuzhiyun #define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1 ) 294*4882a593Smuzhiyun #define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1 ) 295*4882a593Smuzhiyun #define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1 ) 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun #define MPP_MAX 49 298*4882a593Smuzhiyun 299*4882a593Smuzhiyun void kirkwood_mpp_conf(const u32 *mpp_list, u32 *mpp_save); 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun #endif 302