1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2009
3*4882a593Smuzhiyun * Marvell Semiconductor <www.marvell.com>
4*4882a593Smuzhiyun * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #ifndef _KWCPU_H
10*4882a593Smuzhiyun #define _KWCPU_H
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <asm/system.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #ifndef __ASSEMBLY__
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define KWCPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
17*4882a593Smuzhiyun | (attr << 8) | (kw_winctrl_calcsize(size) << 16))
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define KWGBE_PORT_SERIAL_CONTROL1_REG(_x) \
20*4882a593Smuzhiyun ((_x ? KW_EGIGA1_BASE : KW_EGIGA0_BASE) + 0x44c)
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #define KW_REG_PCIE_DEVID (KW_REG_PCIE_BASE + 0x00)
23*4882a593Smuzhiyun #define KW_REG_PCIE_REVID (KW_REG_PCIE_BASE + 0x08)
24*4882a593Smuzhiyun #define KW_REG_DEVICE_ID (KW_MPP_BASE + 0x34)
25*4882a593Smuzhiyun #define KW_REG_SYSRST_CNT (KW_MPP_BASE + 0x50)
26*4882a593Smuzhiyun #define SYSRST_CNT_1SEC_VAL (25*1000000)
27*4882a593Smuzhiyun #define KW_REG_MPP_OUT_DRV_REG (KW_MPP_BASE + 0xE0)
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun enum memory_bank {
30*4882a593Smuzhiyun BANK0,
31*4882a593Smuzhiyun BANK1,
32*4882a593Smuzhiyun BANK2,
33*4882a593Smuzhiyun BANK3
34*4882a593Smuzhiyun };
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun enum kwcpu_winen {
37*4882a593Smuzhiyun KWCPU_WIN_DISABLE,
38*4882a593Smuzhiyun KWCPU_WIN_ENABLE
39*4882a593Smuzhiyun };
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun enum kwcpu_target {
42*4882a593Smuzhiyun KWCPU_TARGET_RESERVED,
43*4882a593Smuzhiyun KWCPU_TARGET_MEMORY,
44*4882a593Smuzhiyun KWCPU_TARGET_1RESERVED,
45*4882a593Smuzhiyun KWCPU_TARGET_SASRAM,
46*4882a593Smuzhiyun KWCPU_TARGET_PCIE
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun enum kwcpu_attrib {
50*4882a593Smuzhiyun KWCPU_ATTR_SASRAM = 0x01,
51*4882a593Smuzhiyun KWCPU_ATTR_DRAM_CS0 = 0x0e,
52*4882a593Smuzhiyun KWCPU_ATTR_DRAM_CS1 = 0x0d,
53*4882a593Smuzhiyun KWCPU_ATTR_DRAM_CS2 = 0x0b,
54*4882a593Smuzhiyun KWCPU_ATTR_DRAM_CS3 = 0x07,
55*4882a593Smuzhiyun KWCPU_ATTR_NANDFLASH = 0x2f,
56*4882a593Smuzhiyun KWCPU_ATTR_SPIFLASH = 0x1e,
57*4882a593Smuzhiyun KWCPU_ATTR_BOOTROM = 0x1d,
58*4882a593Smuzhiyun KWCPU_ATTR_PCIE_IO = 0xe0,
59*4882a593Smuzhiyun KWCPU_ATTR_PCIE_MEM = 0xe8
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun /*
63*4882a593Smuzhiyun * Default Device Address MAP BAR values
64*4882a593Smuzhiyun */
65*4882a593Smuzhiyun #define KW_DEFADR_PCI_MEM 0x90000000
66*4882a593Smuzhiyun #define KW_DEFADR_PCI_IO 0xC0000000
67*4882a593Smuzhiyun #define KW_DEFADR_PCI_IO_REMAP 0xC0000000
68*4882a593Smuzhiyun #define KW_DEFADR_SASRAM 0xC8010000
69*4882a593Smuzhiyun #define KW_DEFADR_NANDF 0xD8000000
70*4882a593Smuzhiyun #define KW_DEFADR_SPIF 0xE8000000
71*4882a593Smuzhiyun #define KW_DEFADR_BOOTROM 0xF8000000
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun /*
74*4882a593Smuzhiyun * read feroceon/sheeva core extra feature register
75*4882a593Smuzhiyun * using co-proc instruction
76*4882a593Smuzhiyun */
readfr_extra_feature_reg(void)77*4882a593Smuzhiyun static inline unsigned int readfr_extra_feature_reg(void)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun unsigned int val;
80*4882a593Smuzhiyun asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr":"=r"
81*4882a593Smuzhiyun (val)::"cc");
82*4882a593Smuzhiyun return val;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun /*
86*4882a593Smuzhiyun * write feroceon/sheeva core extra feature register
87*4882a593Smuzhiyun * using co-proc instruction
88*4882a593Smuzhiyun */
writefr_extra_feature_reg(unsigned int val)89*4882a593Smuzhiyun static inline void writefr_extra_feature_reg(unsigned int val)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr"::"r"
92*4882a593Smuzhiyun (val):"cc");
93*4882a593Smuzhiyun isb();
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun /*
97*4882a593Smuzhiyun * MBus-L to Mbus Bridge Registers
98*4882a593Smuzhiyun * Ref: Datasheet sec:A.3
99*4882a593Smuzhiyun */
100*4882a593Smuzhiyun struct kwwin_registers {
101*4882a593Smuzhiyun u32 ctrl;
102*4882a593Smuzhiyun u32 base;
103*4882a593Smuzhiyun u32 remap_lo;
104*4882a593Smuzhiyun u32 remap_hi;
105*4882a593Smuzhiyun };
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /*
108*4882a593Smuzhiyun * CPU control and status Registers
109*4882a593Smuzhiyun * Ref: Datasheet sec:A.3.2
110*4882a593Smuzhiyun */
111*4882a593Smuzhiyun struct kwcpu_registers {
112*4882a593Smuzhiyun u32 config; /*0x20100 */
113*4882a593Smuzhiyun u32 ctrl_stat; /*0x20104 */
114*4882a593Smuzhiyun u32 rstoutn_mask; /* 0x20108 */
115*4882a593Smuzhiyun u32 sys_soft_rst; /* 0x2010C */
116*4882a593Smuzhiyun u32 ahb_mbus_cause_irq; /* 0x20110 */
117*4882a593Smuzhiyun u32 ahb_mbus_mask_irq; /* 0x20114 */
118*4882a593Smuzhiyun u32 pad1[2];
119*4882a593Smuzhiyun u32 ftdll_config; /* 0x20120 */
120*4882a593Smuzhiyun u32 pad2;
121*4882a593Smuzhiyun u32 l2_cfg; /* 0x20128 */
122*4882a593Smuzhiyun };
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun /*
125*4882a593Smuzhiyun * GPIO Registers
126*4882a593Smuzhiyun * Ref: Datasheet sec:A.19
127*4882a593Smuzhiyun */
128*4882a593Smuzhiyun struct kwgpio_registers {
129*4882a593Smuzhiyun u32 dout;
130*4882a593Smuzhiyun u32 oe;
131*4882a593Smuzhiyun u32 blink_en;
132*4882a593Smuzhiyun u32 din_pol;
133*4882a593Smuzhiyun u32 din;
134*4882a593Smuzhiyun u32 irq_cause;
135*4882a593Smuzhiyun u32 irq_mask;
136*4882a593Smuzhiyun u32 irq_level;
137*4882a593Smuzhiyun };
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun /*
140*4882a593Smuzhiyun * functions
141*4882a593Smuzhiyun */
142*4882a593Smuzhiyun unsigned int mvebu_sdram_bar(enum memory_bank bank);
143*4882a593Smuzhiyun unsigned int mvebu_sdram_bs(enum memory_bank bank);
144*4882a593Smuzhiyun void mvebu_sdram_size_adjust(enum memory_bank bank);
145*4882a593Smuzhiyun int kw_config_adr_windows(void);
146*4882a593Smuzhiyun void mvebu_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
147*4882a593Smuzhiyun unsigned int gpp0_oe, unsigned int gpp1_oe);
148*4882a593Smuzhiyun int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15,
149*4882a593Smuzhiyun unsigned int mpp16_23, unsigned int mpp24_31,
150*4882a593Smuzhiyun unsigned int mpp32_39, unsigned int mpp40_47,
151*4882a593Smuzhiyun unsigned int mpp48_55);
152*4882a593Smuzhiyun unsigned int kw_winctrl_calcsize(unsigned int sizeval);
153*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */
154*4882a593Smuzhiyun #endif /* _KWCPU_H */
155