1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2012-2014
3*4882a593Smuzhiyun * Texas Instruments Incorporated, <www.ti.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun #ifndef _PSC_DEFS_H_
8*4882a593Smuzhiyun #define _PSC_DEFS_H_
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <asm/arch/hardware.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun /*
13*4882a593Smuzhiyun * FILE PURPOSE: Local Power Sleep Controller definitions
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun * FILE NAME: psc_defs.h
16*4882a593Smuzhiyun *
17*4882a593Smuzhiyun * DESCRIPTION: Provides local definitions for the power saver controller
18*4882a593Smuzhiyun *
19*4882a593Smuzhiyun */
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /* Register offsets */
22*4882a593Smuzhiyun #define PSC_REG_PTCMD 0x120
23*4882a593Smuzhiyun #define PSC_REG_PSTAT 0x128
24*4882a593Smuzhiyun #define PSC_REG_PDSTAT(x) (0x200 + (4 * (x)))
25*4882a593Smuzhiyun #define PSC_REG_PDCTL(x) (0x300 + (4 * (x)))
26*4882a593Smuzhiyun #define PSC_REG_MDCFG(x) (0x600 + (4 * (x)))
27*4882a593Smuzhiyun #define PSC_REG_MDSTAT(x) (0x800 + (4 * (x)))
28*4882a593Smuzhiyun #define PSC_REG_MDCTL(x) (0xa00 + (4 * (x)))
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun
_boot_bit_mask(u32 x,u32 y)31*4882a593Smuzhiyun static inline u32 _boot_bit_mask(u32 x, u32 y)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun u32 val = (1 << (x - y + 1)) - 1;
34*4882a593Smuzhiyun return val << y;
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun
boot_read_bitfield(u32 z,u32 x,u32 y)37*4882a593Smuzhiyun static inline u32 boot_read_bitfield(u32 z, u32 x, u32 y)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun u32 val = z & _boot_bit_mask(x, y);
40*4882a593Smuzhiyun return val >> y;
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun
boot_set_bitfield(u32 z,u32 f,u32 x,u32 y)43*4882a593Smuzhiyun static inline u32 boot_set_bitfield(u32 z, u32 f, u32 x, u32 y)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun u32 mask = _boot_bit_mask(x, y);
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun return (z & ~mask) | ((f << y) & mask);
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /* PDCTL */
51*4882a593Smuzhiyun #define PSC_REG_PDCTL_SET_NEXT(x, y) boot_set_bitfield((x), (y), 0, 0)
52*4882a593Smuzhiyun #define PSC_REG_PDCTL_SET_PDMODE(x, y) boot_set_bitfield((x), (y), 15, 12)
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /* PDSTAT */
55*4882a593Smuzhiyun #define PSC_REG_PDSTAT_GET_STATE(x) boot_read_bitfield((x), 4, 0)
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun /* MDCFG */
58*4882a593Smuzhiyun #define PSC_REG_MDCFG_GET_PD(x) boot_read_bitfield((x), 20, 16)
59*4882a593Smuzhiyun #define PSC_REG_MDCFG_GET_RESET_ISO(x) boot_read_bitfield((x), 14, 14)
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /* MDCTL */
62*4882a593Smuzhiyun #define PSC_REG_MDCTL_SET_NEXT(x, y) boot_set_bitfield((x), (y), 4, 0)
63*4882a593Smuzhiyun #define PSC_REG_MDCTL_SET_LRSTZ(x, y) boot_set_bitfield((x), (y), 8, 8)
64*4882a593Smuzhiyun #define PSC_REG_MDCTL_GET_LRSTZ(x) boot_read_bitfield((x), 8, 8)
65*4882a593Smuzhiyun #define PSC_REG_MDCTL_SET_RESET_ISO(x, y) boot_set_bitfield((x), (y), \
66*4882a593Smuzhiyun 12, 12)
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /* MDSTAT */
69*4882a593Smuzhiyun #define PSC_REG_MDSTAT_GET_STATUS(x) boot_read_bitfield((x), 5, 0)
70*4882a593Smuzhiyun #define PSC_REG_MDSTAT_GET_LRSTZ(x) boot_read_bitfield((x), 8, 8)
71*4882a593Smuzhiyun #define PSC_REG_MDSTAT_GET_LRSTDONE(x) boot_read_bitfield((x), 9, 9)
72*4882a593Smuzhiyun #define PSC_REG_MDSTAT_GET_MRSTZ(x) boot_read_bitfield((x), 10, 10)
73*4882a593Smuzhiyun #define PSC_REG_MDSTAT_GET_MRSTDONE(x) boot_read_bitfield((x), 11, 11)
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* PDCTL states */
76*4882a593Smuzhiyun #define PSC_REG_VAL_PDCTL_NEXT_ON 1
77*4882a593Smuzhiyun #define PSC_REG_VAL_PDCTL_NEXT_OFF 0
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun #define PSC_REG_VAL_PDCTL_PDMODE_SLEEP 0
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun /* MDCTL states */
82*4882a593Smuzhiyun #define PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE 0
83*4882a593Smuzhiyun #define PSC_REG_VAL_MDCTL_NEXT_OFF 2
84*4882a593Smuzhiyun #define PSC_REG_VAL_MDCTL_NEXT_ON 3
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun /* MDSTAT states */
87*4882a593Smuzhiyun #define PSC_REG_VAL_MDSTAT_STATE_ON 3
88*4882a593Smuzhiyun #define PSC_REG_VAL_MDSTAT_STATE_ENABLE_IN_PROG 0x24
89*4882a593Smuzhiyun #define PSC_REG_VAL_MDSTAT_STATE_OFF 2
90*4882a593Smuzhiyun #define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG1 0x20
91*4882a593Smuzhiyun #define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG2 0x21
92*4882a593Smuzhiyun #define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG3 0x22
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun /*
95*4882a593Smuzhiyun * Timeout limit on checking PTSTAT. This is the number of times the
96*4882a593Smuzhiyun * wait function will be called before giving up.
97*4882a593Smuzhiyun */
98*4882a593Smuzhiyun #define PSC_PTSTAT_TIMEOUT_LIMIT 100
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun u32 psc_get_domain_num(u32 mod_num);
101*4882a593Smuzhiyun int psc_enable_module(u32 mod_num);
102*4882a593Smuzhiyun int psc_disable_module(u32 mod_num);
103*4882a593Smuzhiyun int psc_disable_domain(u32 domain_num);
104*4882a593Smuzhiyun int psc_module_keep_in_reset_enabled(u32 mod_num, bool gate_clocks);
105*4882a593Smuzhiyun int psc_module_release_from_reset(u32 mod_num);
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun #endif /* _PSC_DEFS_H_ */
108