1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * K2G: Pinmux configuration 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2015 5*4882a593Smuzhiyun * Texas Instruments Incorporated, <www.ti.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __ASM_ARCH_MUX_K2G_H 11*4882a593Smuzhiyun #define __ASM_ARCH_MUX_K2G_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <common.h> 14*4882a593Smuzhiyun #include <asm/io.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define K2G_PADCFG_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x1000) 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* 19*4882a593Smuzhiyun * 20:19 - buffer class RW fixed 20*4882a593Smuzhiyun * 18 - rxactive (Input enabled for the pad ) 0 - Di; 1 - En; 21*4882a593Smuzhiyun * 17 - pulltypesel (0 - PULLDOWN; 1 - PULLUP); 22*4882a593Smuzhiyun * 16 - pulluden (0 - PULLUP/DOWN EN; 1 - DI); 23*4882a593Smuzhiyun * 3:0 - muxmode (available modes 0:5) 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define PIN_IEN (1 << 18) /* pin input enabled */ 27*4882a593Smuzhiyun #define PIN_PDIS (1 << 16) /* pull up/down disabled */ 28*4882a593Smuzhiyun #define PIN_PTU (1 << 17) /* pull up */ 29*4882a593Smuzhiyun #define PIN_PTD (0 << 17) /* pull down */ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define MODE(m) ((m) & 0x7) 32*4882a593Smuzhiyun #define MAX_PIN_N 260 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define MUX_CFG(value, index) \ 35*4882a593Smuzhiyun __raw_writel(\ 36*4882a593Smuzhiyun (value) | \ 37*4882a593Smuzhiyun (__raw_readl(K2G_PADCFG_REG + (index << 2)) & \ 38*4882a593Smuzhiyun (0x3 << 19)),\ 39*4882a593Smuzhiyun (K2G_PADCFG_REG + (index << 2))\ 40*4882a593Smuzhiyun ); 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun struct pin_cfg { 43*4882a593Smuzhiyun int reg_inx; 44*4882a593Smuzhiyun u32 val; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun configure_pin_mux(struct pin_cfg * pin_mux)47*4882a593Smuzhiyunstatic inline void configure_pin_mux(struct pin_cfg *pin_mux) 48*4882a593Smuzhiyun { 49*4882a593Smuzhiyun if (!pin_mux) 50*4882a593Smuzhiyun return; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun while ((pin_mux->reg_inx >= 0) && (pin_mux->reg_inx < MAX_PIN_N)) { 53*4882a593Smuzhiyun MUX_CFG(pin_mux->val, pin_mux->reg_inx); 54*4882a593Smuzhiyun pin_mux++; 55*4882a593Smuzhiyun } 56*4882a593Smuzhiyun } 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #endif /* __ASM_ARCH_MUX_K2G_H */ 59