1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * K2L: SoC definitions 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2012-2014 5*4882a593Smuzhiyun * Texas Instruments Incorporated, <www.ti.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __ASM_ARCH_HARDWARE_K2L_H 11*4882a593Smuzhiyun #define __ASM_ARCH_HARDWARE_K2L_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define KS2_ARM_PLL_EN BIT(13) 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* PA SS Registers */ 16*4882a593Smuzhiyun #define KS2_PASS_BASE 0x26000000 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* Power and Sleep Controller (PSC) Domains */ 19*4882a593Smuzhiyun #define KS2_LPSC_MOD 0 20*4882a593Smuzhiyun #define KS2_LPSC_DFE_IQN_SYS 1 21*4882a593Smuzhiyun #define KS2_LPSC_USB 2 22*4882a593Smuzhiyun #define KS2_LPSC_EMIF25_SPI 3 23*4882a593Smuzhiyun #define KS2_LPSC_TSIP 4 24*4882a593Smuzhiyun #define KS2_LPSC_DEBUGSS_TRC 5 25*4882a593Smuzhiyun #define KS2_LPSC_TETB_TRC 6 26*4882a593Smuzhiyun #define KS2_LPSC_PKTPROC 7 27*4882a593Smuzhiyun #define KS2_LPSC_PA KS2_LPSC_PKTPROC 28*4882a593Smuzhiyun #define KS2_LPSC_SGMII 8 29*4882a593Smuzhiyun #define KS2_LPSC_CPGMAC KS2_LPSC_SGMII 30*4882a593Smuzhiyun #define KS2_LPSC_CRYPTO 9 31*4882a593Smuzhiyun #define KS2_LPSC_PCIE0 10 32*4882a593Smuzhiyun #define KS2_LPSC_PCIE1 11 33*4882a593Smuzhiyun #define KS2_LPSC_JESD_MISC 12 34*4882a593Smuzhiyun #define KS2_LPSC_CHIP_SRSS 13 35*4882a593Smuzhiyun #define KS2_LPSC_MSMC 14 36*4882a593Smuzhiyun #define KS2_LPSC_GEM_1 16 37*4882a593Smuzhiyun #define KS2_LPSC_GEM_2 17 38*4882a593Smuzhiyun #define KS2_LPSC_GEM_3 18 39*4882a593Smuzhiyun #define KS2_LPSC_EMIF4F_DDR3 23 40*4882a593Smuzhiyun #define KS2_LPSC_TAC 25 41*4882a593Smuzhiyun #define KS2_LPSC_RAC 26 42*4882a593Smuzhiyun #define KS2_LPSC_DDUC4X_CFR2X_BB 27 43*4882a593Smuzhiyun #define KS2_LPSC_FFTC_A 28 44*4882a593Smuzhiyun #define KS2_LPSC_OSR 34 45*4882a593Smuzhiyun #define KS2_LPSC_TCP3D_0 35 46*4882a593Smuzhiyun #define KS2_LPSC_TCP3D_1 37 47*4882a593Smuzhiyun #define KS2_LPSC_VCP2X4_A 39 48*4882a593Smuzhiyun #define KS2_LPSC_VCP2X4_B 40 49*4882a593Smuzhiyun #define KS2_LPSC_VCP2X4_C 41 50*4882a593Smuzhiyun #define KS2_LPSC_VCP2X4_D 42 51*4882a593Smuzhiyun #define KS2_LPSC_BCP 47 52*4882a593Smuzhiyun #define KS2_LPSC_DPD4X 48 53*4882a593Smuzhiyun #define KS2_LPSC_FFTC_B 49 54*4882a593Smuzhiyun #define KS2_LPSC_IQN_AIL 50 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* Chip Interrupt Controller */ 57*4882a593Smuzhiyun #define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3 58*4882a593Smuzhiyun #define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* OSR */ 61*4882a593Smuzhiyun #define KS2_OSR_DATA_BASE 0x70000000 /* OSR data base */ 62*4882a593Smuzhiyun #define KS2_OSR_CFG_BASE 0x02348c00 /* OSR config base */ 63*4882a593Smuzhiyun #define KS2_OSR_ECC_VEC 0x08 /* ECC Vector reg */ 64*4882a593Smuzhiyun #define KS2_OSR_ECC_CTRL 0x14 /* ECC control reg */ 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* OSR ECC Vector register */ 67*4882a593Smuzhiyun #define KS2_OSR_ECC_VEC_TRIG_RD BIT(15) /* trigger a read op */ 68*4882a593Smuzhiyun #define KS2_OSR_ECC_VEC_RD_DONE BIT(24) /* read complete */ 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define KS2_OSR_ECC_VEC_RAM_ID_SH 0 /* RAM ID shift */ 71*4882a593Smuzhiyun #define KS2_OSR_ECC_VEC_RD_ADDR_SH 16 /* read address shift */ 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* OSR ECC control register */ 74*4882a593Smuzhiyun #define KS2_OSR_ECC_CTRL_EN BIT(0) /* ECC enable bit */ 75*4882a593Smuzhiyun #define KS2_OSR_ECC_CTRL_CHK BIT(1) /* ECC check bit */ 76*4882a593Smuzhiyun #define KS2_OSR_ECC_CTRL_RMW BIT(2) /* ECC check bit */ 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* Number of OSR RAM banks */ 79*4882a593Smuzhiyun #define KS2_OSR_NUM_RAM_BANKS 4 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* OSR memory size */ 82*4882a593Smuzhiyun #define KS2_OSR_SIZE 0x100000 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* SGMII SerDes */ 85*4882a593Smuzhiyun #define KS2_SGMII_SERDES2_BASE 0x02320000 86*4882a593Smuzhiyun #define KS2_LANES_PER_SGMII_SERDES 2 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* Number of DSP cores */ 89*4882a593Smuzhiyun #define KS2_NUM_DSPS 4 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* NETCP pktdma */ 92*4882a593Smuzhiyun #define KS2_NETCP_PDMA_CTRL_BASE 0x26186000 93*4882a593Smuzhiyun #define KS2_NETCP_PDMA_TX_BASE 0x26187000 94*4882a593Smuzhiyun #define KS2_NETCP_PDMA_TX_CH_NUM 21 95*4882a593Smuzhiyun #define KS2_NETCP_PDMA_RX_BASE 0x26188000 96*4882a593Smuzhiyun #define KS2_NETCP_PDMA_RX_CH_NUM 91 97*4882a593Smuzhiyun #define KS2_NETCP_PDMA_SCHED_BASE 0x26186100 98*4882a593Smuzhiyun #define KS2_NETCP_PDMA_RX_FLOW_BASE 0x26189000 99*4882a593Smuzhiyun #define KS2_NETCP_PDMA_RX_FLOW_NUM 96 100*4882a593Smuzhiyun #define KS2_NETCP_PDMA_TX_SND_QUEUE 896 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* NETCP */ 103*4882a593Smuzhiyun #define KS2_NETCP_BASE 0x26000000 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #ifndef __ASSEMBLY__ ddr3_get_size(void)106*4882a593Smuzhiyunstatic inline int ddr3_get_size(void) 107*4882a593Smuzhiyun { 108*4882a593Smuzhiyun return 2; 109*4882a593Smuzhiyun } 110*4882a593Smuzhiyun #endif 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #endif /* __ASM_ARCH_HARDWARE_K2L_H */ 113