1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * K2HK: SoC definitions 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2012-2014 5*4882a593Smuzhiyun * Texas Instruments Incorporated, <www.ti.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __ASM_ARCH_HARDWARE_K2HK_H 11*4882a593Smuzhiyun #define __ASM_ARCH_HARDWARE_K2HK_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define KS2_ARM_PLL_EN BIT(13) 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* PA SS Registers */ 16*4882a593Smuzhiyun #define KS2_PASS_BASE 0x02000000 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* Power and Sleep Controller (PSC) Domains */ 19*4882a593Smuzhiyun #define KS2_LPSC_MOD 0 20*4882a593Smuzhiyun #define KS2_LPSC_DUMMY1 1 21*4882a593Smuzhiyun #define KS2_LPSC_USB 2 22*4882a593Smuzhiyun #define KS2_LPSC_EMIF25_SPI 3 23*4882a593Smuzhiyun #define KS2_LPSC_TSIP 4 24*4882a593Smuzhiyun #define KS2_LPSC_DEBUGSS_TRC 5 25*4882a593Smuzhiyun #define KS2_LPSC_TETB_TRC 6 26*4882a593Smuzhiyun #define KS2_LPSC_PKTPROC 7 27*4882a593Smuzhiyun #define KS2_LPSC_PA KS2_LPSC_PKTPROC 28*4882a593Smuzhiyun #define KS2_LPSC_SGMII 8 29*4882a593Smuzhiyun #define KS2_LPSC_CPGMAC KS2_LPSC_SGMII 30*4882a593Smuzhiyun #define KS2_LPSC_CRYPTO 9 31*4882a593Smuzhiyun #define KS2_LPSC_PCIE 10 32*4882a593Smuzhiyun #define KS2_LPSC_SRIO 11 33*4882a593Smuzhiyun #define KS2_LPSC_VUSR0 12 34*4882a593Smuzhiyun #define KS2_LPSC_CHIP_SRSS 13 35*4882a593Smuzhiyun #define KS2_LPSC_MSMC 14 36*4882a593Smuzhiyun #define KS2_LPSC_GEM_1 16 37*4882a593Smuzhiyun #define KS2_LPSC_GEM_2 17 38*4882a593Smuzhiyun #define KS2_LPSC_GEM_3 18 39*4882a593Smuzhiyun #define KS2_LPSC_GEM_4 19 40*4882a593Smuzhiyun #define KS2_LPSC_GEM_5 20 41*4882a593Smuzhiyun #define KS2_LPSC_GEM_6 21 42*4882a593Smuzhiyun #define KS2_LPSC_GEM_7 22 43*4882a593Smuzhiyun #define KS2_LPSC_EMIF4F_DDR3A 23 44*4882a593Smuzhiyun #define KS2_LPSC_EMIF4F_DDR3B 24 45*4882a593Smuzhiyun #define KS2_LPSC_TAC 25 46*4882a593Smuzhiyun #define KS2_LPSC_RAC 26 47*4882a593Smuzhiyun #define KS2_LPSC_RAC_1 27 48*4882a593Smuzhiyun #define KS2_LPSC_FFTC_A 28 49*4882a593Smuzhiyun #define KS2_LPSC_FFTC_B 29 50*4882a593Smuzhiyun #define KS2_LPSC_FFTC_C 30 51*4882a593Smuzhiyun #define KS2_LPSC_FFTC_D 31 52*4882a593Smuzhiyun #define KS2_LPSC_FFTC_E 32 53*4882a593Smuzhiyun #define KS2_LPSC_FFTC_F 33 54*4882a593Smuzhiyun #define KS2_LPSC_AI2 34 55*4882a593Smuzhiyun #define KS2_LPSC_TCP3D_0 35 56*4882a593Smuzhiyun #define KS2_LPSC_TCP3D_1 36 57*4882a593Smuzhiyun #define KS2_LPSC_TCP3D_2 37 58*4882a593Smuzhiyun #define KS2_LPSC_TCP3D_3 38 59*4882a593Smuzhiyun #define KS2_LPSC_VCP2X4_A 39 60*4882a593Smuzhiyun #define KS2_LPSC_CP2X4_B 40 61*4882a593Smuzhiyun #define KS2_LPSC_VCP2X4_C 41 62*4882a593Smuzhiyun #define KS2_LPSC_VCP2X4_D 42 63*4882a593Smuzhiyun #define KS2_LPSC_VCP2X4_E 43 64*4882a593Smuzhiyun #define KS2_LPSC_VCP2X4_F 44 65*4882a593Smuzhiyun #define KS2_LPSC_VCP2X4_G 45 66*4882a593Smuzhiyun #define KS2_LPSC_VCP2X4_H 46 67*4882a593Smuzhiyun #define KS2_LPSC_BCP 47 68*4882a593Smuzhiyun #define KS2_LPSC_DXB 48 69*4882a593Smuzhiyun #define KS2_LPSC_VUSR1 49 70*4882a593Smuzhiyun #define KS2_LPSC_XGE 50 71*4882a593Smuzhiyun #define KS2_LPSC_ARM_SREFLEX 51 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* DDR3B definitions */ 74*4882a593Smuzhiyun #define KS2_DDR3B_EMIF_CTRL_BASE 0x21020000 75*4882a593Smuzhiyun #define KS2_DDR3B_EMIF_DATA_BASE 0x60000000 76*4882a593Smuzhiyun #define KS2_DDR3B_DDRPHYC 0x02328000 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3 /* DDR3 ECC system irq number */ 79*4882a593Smuzhiyun #define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D /* DDR3 ECC int mapped to CIC2 80*4882a593Smuzhiyun channel 29 */ 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* SGMII SerDes */ 83*4882a593Smuzhiyun #define KS2_LANES_PER_SGMII_SERDES 4 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* Number of DSP cores */ 86*4882a593Smuzhiyun #define KS2_NUM_DSPS 8 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* NETCP pktdma */ 89*4882a593Smuzhiyun #define KS2_NETCP_PDMA_CTRL_BASE 0x02004000 90*4882a593Smuzhiyun #define KS2_NETCP_PDMA_TX_BASE 0x02004400 91*4882a593Smuzhiyun #define KS2_NETCP_PDMA_TX_CH_NUM 9 92*4882a593Smuzhiyun #define KS2_NETCP_PDMA_RX_BASE 0x02004800 93*4882a593Smuzhiyun #define KS2_NETCP_PDMA_RX_CH_NUM 26 94*4882a593Smuzhiyun #define KS2_NETCP_PDMA_SCHED_BASE 0x02004c00 95*4882a593Smuzhiyun #define KS2_NETCP_PDMA_RX_FLOW_BASE 0x02005000 96*4882a593Smuzhiyun #define KS2_NETCP_PDMA_RX_FLOW_NUM 32 97*4882a593Smuzhiyun #define KS2_NETCP_PDMA_TX_SND_QUEUE 648 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun /* NETCP */ 100*4882a593Smuzhiyun #define KS2_NETCP_BASE 0x02000000 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #endif /* __ASM_ARCH_HARDWARE_H */ 103