1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * K2G: SoC definitions 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2015 5*4882a593Smuzhiyun * Texas Instruments Incorporated, <www.ti.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __ASM_ARCH_HARDWARE_K2G_H 11*4882a593Smuzhiyun #define __ASM_ARCH_HARDWARE_K2G_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define KS2_NUM_DSPS 1 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* Power and Sleep Controller (PSC) Domains */ 16*4882a593Smuzhiyun #define KS2_LPSC_ALWAYSON 0 17*4882a593Smuzhiyun #define KS2_LPSC_PMMC 1 18*4882a593Smuzhiyun #define KS2_LPSC_DEBUG 2 19*4882a593Smuzhiyun #define KS2_LPSC_NSS 3 20*4882a593Smuzhiyun #define KS2_LPSC_SA 4 21*4882a593Smuzhiyun #define KS2_LPSC_TERANET 5 22*4882a593Smuzhiyun #define KS2_LPSC_SYS_COMP 6 23*4882a593Smuzhiyun #define KS2_LPSC_QSPI 7 24*4882a593Smuzhiyun #define KS2_LPSC_MMC 8 25*4882a593Smuzhiyun #define KS2_LPSC_GPMC 9 26*4882a593Smuzhiyun #define KS2_LPSC_MLB 11 27*4882a593Smuzhiyun #define KS2_LPSC_EHRPWM 12 28*4882a593Smuzhiyun #define KS2_LPSC_EQEP 13 29*4882a593Smuzhiyun #define KS2_LPSC_ECAP 14 30*4882a593Smuzhiyun #define KS2_LPSC_MCASP 15 31*4882a593Smuzhiyun #define KS2_LPSC_SR 16 32*4882a593Smuzhiyun #define KS2_LPSC_MSMC 17 33*4882a593Smuzhiyun #ifdef KS2_LPSC_GEM_0 34*4882a593Smuzhiyun #undef KS2_LPSC_GEM_0 35*4882a593Smuzhiyun #endif 36*4882a593Smuzhiyun #define KS2_LPSC_GEM_0 18 37*4882a593Smuzhiyun #define KS2_LPSC_ARM 19 38*4882a593Smuzhiyun #define KS2_LPSC_ASRC 20 39*4882a593Smuzhiyun #define KS2_LPSC_ICSS 21 40*4882a593Smuzhiyun #define KS2_LPSC_DSS 23 41*4882a593Smuzhiyun #define KS2_LPSC_PCIE 24 42*4882a593Smuzhiyun #define KS2_LPSC_USB_0 25 43*4882a593Smuzhiyun #define KS2_LPSC_USB KS2_LPSC_USB_0 44*4882a593Smuzhiyun #define KS2_LPSC_USB_1 26 45*4882a593Smuzhiyun #define KS2_LPSC_DDR3 27 46*4882a593Smuzhiyun #define KS2_LPSC_SPARE0_LPSC0 28 47*4882a593Smuzhiyun #define KS2_LPSC_SPARE0_LPSC1 29 48*4882a593Smuzhiyun #define KS2_LPSC_SPARE1_LPSC0 30 49*4882a593Smuzhiyun #define KS2_LPSC_SPARE1_LPSC1 31 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define KS2_LPSC_CPGMAC KS2_LPSC_NSS 52*4882a593Smuzhiyun #define KS2_LPSC_CRYPTO KS2_LPSC_SA 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* SGMII SerDes */ 55*4882a593Smuzhiyun #define KS2_LANES_PER_SGMII_SERDES 4 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* NETCP pktdma */ 58*4882a593Smuzhiyun #define KS2_NETCP_PDMA_CTRL_BASE 0x04010000 59*4882a593Smuzhiyun #define KS2_NETCP_PDMA_TX_BASE 0x04011000 60*4882a593Smuzhiyun #define KS2_NETCP_PDMA_TX_CH_NUM 21 61*4882a593Smuzhiyun #define KS2_NETCP_PDMA_RX_BASE 0x04012000 62*4882a593Smuzhiyun #define KS2_NETCP_PDMA_RX_CH_NUM 32 63*4882a593Smuzhiyun #define KS2_NETCP_PDMA_SCHED_BASE 0x04010100 64*4882a593Smuzhiyun #define KS2_NETCP_PDMA_RX_FLOW_BASE 0x04013000 65*4882a593Smuzhiyun #define KS2_NETCP_PDMA_RX_FLOW_NUM 32 66*4882a593Smuzhiyun #define KS2_NETCP_PDMA_TX_SND_QUEUE 5 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* NETCP */ 69*4882a593Smuzhiyun #define KS2_NETCP_BASE 0x04000000 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define K2G_GPIO0_BASE 0X02603000 72*4882a593Smuzhiyun #define K2G_GPIO1_BASE 0X0260a000 73*4882a593Smuzhiyun #define K2G_GPIO1_BANK2_BASE K2G_GPIO1_BASE + 0x38 74*4882a593Smuzhiyun #define K2G_GPIO_DIR_OFFSET 0x0 75*4882a593Smuzhiyun #define K2G_GPIO_SETDATA_OFFSET 0x8 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* BOOTCFG RESETMUX8 */ 78*4882a593Smuzhiyun #define KS2_RSTMUX8 (KS2_DEVICE_STATE_CTRL_BASE + 0x328) 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* RESETMUX register definitions */ 81*4882a593Smuzhiyun #define RSTMUX_LOCK8_SHIFT 0x0 82*4882a593Smuzhiyun #define RSTMUX_LOCK8_MASK (0x1 << 0) 83*4882a593Smuzhiyun #define RSTMUX_OMODE8_SHIFT 0x1 84*4882a593Smuzhiyun #define RSTMUX_OMODE8_MASK (0x7 << 1) 85*4882a593Smuzhiyun #define RSTMUX_OMODE8_DEV_RESET 0x2 86*4882a593Smuzhiyun #define RSTMUX_OMODE8_INT 0x3 87*4882a593Smuzhiyun #define RSTMUX_OMODE8_INT_AND_DEV_RESET 0x4 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* DEVSTAT register definition */ 90*4882a593Smuzhiyun #define KS2_DEVSTAT_REFCLK_SHIFT 7 91*4882a593Smuzhiyun #define KS2_DEVSTAT_REFCLK_MASK (0x7 << 7) 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* GPMC */ 94*4882a593Smuzhiyun #define KS2_GPMC_BASE 0x21818000 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* SYSCLK indexes */ 97*4882a593Smuzhiyun #define SYSCLK_19MHz 0 98*4882a593Smuzhiyun #define SYSCLK_24MHz 1 99*4882a593Smuzhiyun #define SYSCLK_25MHz 2 100*4882a593Smuzhiyun #define SYSCLK_26MHz 3 101*4882a593Smuzhiyun #define MAX_SYSCLK 4 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #ifndef __ASSEMBLY__ get_sysclk_index(void)104*4882a593Smuzhiyunstatic inline u8 get_sysclk_index(void) 105*4882a593Smuzhiyun { 106*4882a593Smuzhiyun u32 dev_stat = __raw_readl(KS2_DEVSTAT); 107*4882a593Smuzhiyun return (dev_stat & KS2_DEVSTAT_REFCLK_MASK) >> KS2_DEVSTAT_REFCLK_SHIFT; 108*4882a593Smuzhiyun } 109*4882a593Smuzhiyun #endif 110*4882a593Smuzhiyun #endif /* __ASM_ARCH_HARDWARE_K2G_H */ 111