1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * K2E: SoC definitions 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2012-2014 5*4882a593Smuzhiyun * Texas Instruments Incorporated, <www.ti.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __ASM_ARCH_HARDWARE_K2E_H 11*4882a593Smuzhiyun #define __ASM_ARCH_HARDWARE_K2E_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* PA SS Registers */ 14*4882a593Smuzhiyun #define KS2_PASS_BASE 0x24000000 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* Power and Sleep Controller (PSC) Domains */ 17*4882a593Smuzhiyun #define KS2_LPSC_MOD_RST 0 18*4882a593Smuzhiyun #define KS2_LPSC_USB_1 1 19*4882a593Smuzhiyun #define KS2_LPSC_USB 2 20*4882a593Smuzhiyun #define KS2_LPSC_EMIF25_SPI 3 21*4882a593Smuzhiyun #define KS2_LPSC_TSIP 4 22*4882a593Smuzhiyun #define KS2_LPSC_DEBUGSS_TRC 5 23*4882a593Smuzhiyun #define KS2_LPSC_TETB_TRC 6 24*4882a593Smuzhiyun #define KS2_LPSC_PKTPROC 7 25*4882a593Smuzhiyun #define KS2_LPSC_PA KS2_LPSC_PKTPROC 26*4882a593Smuzhiyun #define KS2_LPSC_SGMII 8 27*4882a593Smuzhiyun #define KS2_LPSC_CPGMAC KS2_LPSC_SGMII 28*4882a593Smuzhiyun #define KS2_LPSC_CRYPTO 9 29*4882a593Smuzhiyun #define KS2_LPSC_PCIE 10 30*4882a593Smuzhiyun #define KS2_LPSC_VUSR0 12 31*4882a593Smuzhiyun #define KS2_LPSC_CHIP_SRSS 13 32*4882a593Smuzhiyun #define KS2_LPSC_MSMC 14 33*4882a593Smuzhiyun #define KS2_LPSC_EMIF4F_DDR3 23 34*4882a593Smuzhiyun #define KS2_LPSC_PCIE_1 27 35*4882a593Smuzhiyun #define KS2_LPSC_XGE 50 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* Chip Interrupt Controller */ 38*4882a593Smuzhiyun #define KS2_CIC2_DDR3_ECC_IRQ_NUM -1 /* not defined in K2E */ 39*4882a593Smuzhiyun #define KS2_CIC2_DDR3_ECC_CHAN_NUM -1 /* not defined in K2E */ 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* SGMII SerDes */ 42*4882a593Smuzhiyun #define KS2_SGMII_SERDES2_BASE 0x02324000 43*4882a593Smuzhiyun #define KS2_LANES_PER_SGMII_SERDES 4 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* Number of DSP cores */ 46*4882a593Smuzhiyun #define KS2_NUM_DSPS 1 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* NETCP pktdma */ 49*4882a593Smuzhiyun #define KS2_NETCP_PDMA_CTRL_BASE 0x24186000 50*4882a593Smuzhiyun #define KS2_NETCP_PDMA_TX_BASE 0x24187000 51*4882a593Smuzhiyun #define KS2_NETCP_PDMA_TX_CH_NUM 21 52*4882a593Smuzhiyun #define KS2_NETCP_PDMA_RX_BASE 0x24188000 53*4882a593Smuzhiyun #define KS2_NETCP_PDMA_RX_CH_NUM 91 54*4882a593Smuzhiyun #define KS2_NETCP_PDMA_SCHED_BASE 0x24186100 55*4882a593Smuzhiyun #define KS2_NETCP_PDMA_RX_FLOW_BASE 0x24189000 56*4882a593Smuzhiyun #define KS2_NETCP_PDMA_RX_FLOW_NUM 96 57*4882a593Smuzhiyun #define KS2_NETCP_PDMA_TX_SND_QUEUE 896 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* NETCP */ 60*4882a593Smuzhiyun #define KS2_NETCP_BASE 0x24000000 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #endif 63