1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * keystone2: common clock header file 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2012-2014 5*4882a593Smuzhiyun * Texas Instruments Incorporated, <www.ti.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __ASM_ARCH_CLOCK_H 11*4882a593Smuzhiyun #define __ASM_ARCH_CLOCK_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #ifdef CONFIG_SOC_K2HK 16*4882a593Smuzhiyun #include <asm/arch/clock-k2hk.h> 17*4882a593Smuzhiyun #endif 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #ifdef CONFIG_SOC_K2E 20*4882a593Smuzhiyun #include <asm/arch/clock-k2e.h> 21*4882a593Smuzhiyun #endif 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #ifdef CONFIG_SOC_K2L 24*4882a593Smuzhiyun #include <asm/arch/clock-k2l.h> 25*4882a593Smuzhiyun #endif 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #ifdef CONFIG_SOC_K2G 28*4882a593Smuzhiyun #include <asm/arch/clock-k2g.h> 29*4882a593Smuzhiyun #endif 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define CORE_PLL MAIN_PLL 32*4882a593Smuzhiyun #define DDR3_PLL DDR3A_PLL 33*4882a593Smuzhiyun #define NSS_PLL PASS_PLL 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define CLK_LIST(CLK)\ 36*4882a593Smuzhiyun CLK(0, core_pll_clk)\ 37*4882a593Smuzhiyun CLK(1, pass_pll_clk)\ 38*4882a593Smuzhiyun CLK(2, tetris_pll_clk)\ 39*4882a593Smuzhiyun CLK(3, ddr3a_pll_clk)\ 40*4882a593Smuzhiyun CLK(4, ddr3b_pll_clk)\ 41*4882a593Smuzhiyun CLK(5, sys_clk0_clk)\ 42*4882a593Smuzhiyun CLK(6, sys_clk0_1_clk)\ 43*4882a593Smuzhiyun CLK(7, sys_clk0_2_clk)\ 44*4882a593Smuzhiyun CLK(8, sys_clk0_3_clk)\ 45*4882a593Smuzhiyun CLK(9, sys_clk0_4_clk)\ 46*4882a593Smuzhiyun CLK(10, sys_clk0_6_clk)\ 47*4882a593Smuzhiyun CLK(11, sys_clk0_8_clk)\ 48*4882a593Smuzhiyun CLK(12, sys_clk0_12_clk)\ 49*4882a593Smuzhiyun CLK(13, sys_clk0_24_clk)\ 50*4882a593Smuzhiyun CLK(14, sys_clk1_clk)\ 51*4882a593Smuzhiyun CLK(15, sys_clk1_3_clk)\ 52*4882a593Smuzhiyun CLK(16, sys_clk1_4_clk)\ 53*4882a593Smuzhiyun CLK(17, sys_clk1_6_clk)\ 54*4882a593Smuzhiyun CLK(18, sys_clk1_12_clk)\ 55*4882a593Smuzhiyun CLK(19, sys_clk2_clk)\ 56*4882a593Smuzhiyun CLK(20, sys_clk3_clk)\ 57*4882a593Smuzhiyun CLK(21, uart_pll_clk) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #include <asm/types.h> 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define GENERATE_ENUM(NUM, ENUM) ENUM = NUM, 62*4882a593Smuzhiyun #define GENERATE_INDX_STR(NUM, STRING) #NUM"\t- "#STRING"\n" 63*4882a593Smuzhiyun #define CLOCK_INDEXES_LIST CLK_LIST(GENERATE_INDX_STR) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun enum { 66*4882a593Smuzhiyun SPD200, 67*4882a593Smuzhiyun SPD400, 68*4882a593Smuzhiyun SPD600, 69*4882a593Smuzhiyun SPD800, 70*4882a593Smuzhiyun SPD850, 71*4882a593Smuzhiyun SPD900, 72*4882a593Smuzhiyun SPD1000, 73*4882a593Smuzhiyun SPD1200, 74*4882a593Smuzhiyun SPD1250, 75*4882a593Smuzhiyun SPD1350, 76*4882a593Smuzhiyun SPD1400, 77*4882a593Smuzhiyun SPD1500, 78*4882a593Smuzhiyun NUM_SPDS, 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* PLL identifiers */ 82*4882a593Smuzhiyun enum { 83*4882a593Smuzhiyun MAIN_PLL, 84*4882a593Smuzhiyun TETRIS_PLL, 85*4882a593Smuzhiyun PASS_PLL, 86*4882a593Smuzhiyun DDR3A_PLL, 87*4882a593Smuzhiyun DDR3B_PLL, 88*4882a593Smuzhiyun UART_PLL, 89*4882a593Smuzhiyun MAX_PLL_COUNT, 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun enum ext_clk_e { 93*4882a593Smuzhiyun sys_clk, 94*4882a593Smuzhiyun alt_core_clk, 95*4882a593Smuzhiyun pa_clk, 96*4882a593Smuzhiyun tetris_clk, 97*4882a593Smuzhiyun ddr3a_clk, 98*4882a593Smuzhiyun ddr3b_clk, 99*4882a593Smuzhiyun uart_clk, 100*4882a593Smuzhiyun ext_clk_count /* number of external clocks */ 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun enum clk_e { 104*4882a593Smuzhiyun CLK_LIST(GENERATE_ENUM) 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun struct keystone_pll_regs { 108*4882a593Smuzhiyun u32 reg0; 109*4882a593Smuzhiyun u32 reg1; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /* PLL configuration data */ 113*4882a593Smuzhiyun struct pll_init_data { 114*4882a593Smuzhiyun int pll; 115*4882a593Smuzhiyun int pll_m; /* PLL Multiplier */ 116*4882a593Smuzhiyun int pll_d; /* PLL divider */ 117*4882a593Smuzhiyun int pll_od; /* PLL output divider */ 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun extern const struct keystone_pll_regs keystone_pll_regs[]; 121*4882a593Smuzhiyun extern s16 divn_val[]; 122*4882a593Smuzhiyun extern int speeds[]; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun void init_plls(void); 125*4882a593Smuzhiyun void init_pll(const struct pll_init_data *data); 126*4882a593Smuzhiyun struct pll_init_data *get_pll_init_data(int pll); 127*4882a593Smuzhiyun unsigned long ks_clk_get_rate(unsigned int clk); 128*4882a593Smuzhiyun int get_max_dev_speed(int *spds); 129*4882a593Smuzhiyun int get_max_arm_speed(int *spds); 130*4882a593Smuzhiyun void pll_pa_clk_sel(void); 131*4882a593Smuzhiyun unsigned int get_external_clk(u32 clk); 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun #endif 134*4882a593Smuzhiyun #endif 135