1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2007
3*4882a593Smuzhiyun * Sascha Hauer, Pengutronix
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * (C) Copyright 2009 Freescale Semiconductor, Inc.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <asm/io.h>
12*4882a593Smuzhiyun #include <div64.h>
13*4882a593Smuzhiyun #include <asm/arch/imx-regs.h>
14*4882a593Smuzhiyun #include <asm/arch/clock.h>
15*4882a593Smuzhiyun #include <asm/arch/sys_proto.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun /* General purpose timers registers */
18*4882a593Smuzhiyun struct mxc_gpt {
19*4882a593Smuzhiyun unsigned int control;
20*4882a593Smuzhiyun unsigned int prescaler;
21*4882a593Smuzhiyun unsigned int status;
22*4882a593Smuzhiyun unsigned int nouse[6];
23*4882a593Smuzhiyun unsigned int counter;
24*4882a593Smuzhiyun };
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* General purpose timers bitfields */
29*4882a593Smuzhiyun #define GPTCR_SWR (1 << 15) /* Software reset */
30*4882a593Smuzhiyun #define GPTCR_24MEN (1 << 10) /* Enable 24MHz clock input */
31*4882a593Smuzhiyun #define GPTCR_FRR (1 << 9) /* Freerun / restart */
32*4882a593Smuzhiyun #define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source 32khz */
33*4882a593Smuzhiyun #define GPTCR_CLKSOURCE_OSC (5 << 6) /* Clock source OSC */
34*4882a593Smuzhiyun #define GPTCR_CLKSOURCE_PRE (1 << 6) /* Clock source PRECLK */
35*4882a593Smuzhiyun #define GPTCR_CLKSOURCE_MASK (0x7 << 6)
36*4882a593Smuzhiyun #define GPTCR_TEN 1 /* Timer enable */
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #define GPTPR_PRESCALER24M_SHIFT 12
39*4882a593Smuzhiyun #define GPTPR_PRESCALER24M_MASK (0xF << GPTPR_PRESCALER24M_SHIFT)
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
42*4882a593Smuzhiyun
gpt_has_clk_source_osc(void)43*4882a593Smuzhiyun static inline int gpt_has_clk_source_osc(void)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun #if defined(CONFIG_MX6)
46*4882a593Smuzhiyun if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) ||
47*4882a593Smuzhiyun is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul() ||
48*4882a593Smuzhiyun is_mx6ull() || is_mx6sll())
49*4882a593Smuzhiyun return 1;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun return 0;
52*4882a593Smuzhiyun #else
53*4882a593Smuzhiyun return 0;
54*4882a593Smuzhiyun #endif
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
gpt_get_clk(void)57*4882a593Smuzhiyun static inline ulong gpt_get_clk(void)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun #ifdef CONFIG_MXC_GPT_HCLK
60*4882a593Smuzhiyun if (gpt_has_clk_source_osc())
61*4882a593Smuzhiyun return MXC_HCLK >> 3;
62*4882a593Smuzhiyun else
63*4882a593Smuzhiyun return mxc_get_clock(MXC_IPG_PERCLK);
64*4882a593Smuzhiyun #else
65*4882a593Smuzhiyun return MXC_CLK32;
66*4882a593Smuzhiyun #endif
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
timer_init(void)69*4882a593Smuzhiyun int timer_init(void)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun int i;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun /* setup GP Timer 1 */
74*4882a593Smuzhiyun __raw_writel(GPTCR_SWR, &cur_gpt->control);
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun /* We have no udelay by now */
77*4882a593Smuzhiyun __raw_writel(0, &cur_gpt->control);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun i = __raw_readl(&cur_gpt->control);
80*4882a593Smuzhiyun i &= ~GPTCR_CLKSOURCE_MASK;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun #ifdef CONFIG_MXC_GPT_HCLK
83*4882a593Smuzhiyun if (gpt_has_clk_source_osc()) {
84*4882a593Smuzhiyun i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun /*
87*4882a593Smuzhiyun * For DL/S, SX, UL, ULL, SLL set 24Mhz OSC
88*4882a593Smuzhiyun * Enable bit and prescaler
89*4882a593Smuzhiyun */
90*4882a593Smuzhiyun if (is_mx6sdl() || is_mx6sx() || is_mx6ul() || is_mx6ull() ||
91*4882a593Smuzhiyun is_mx6sll()) {
92*4882a593Smuzhiyun i |= GPTCR_24MEN;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun /* Produce 3Mhz clock */
95*4882a593Smuzhiyun __raw_writel((7 << GPTPR_PRESCALER24M_SHIFT),
96*4882a593Smuzhiyun &cur_gpt->prescaler);
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun } else {
99*4882a593Smuzhiyun i |= GPTCR_CLKSOURCE_PRE | GPTCR_TEN;
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun #else
102*4882a593Smuzhiyun __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */
103*4882a593Smuzhiyun i |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
104*4882a593Smuzhiyun #endif
105*4882a593Smuzhiyun __raw_writel(i, &cur_gpt->control);
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun return 0;
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun
timer_read_counter(void)110*4882a593Smuzhiyun unsigned long timer_read_counter(void)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun return __raw_readl(&cur_gpt->counter); /* current tick value */
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun /*
116*4882a593Smuzhiyun * This function is derived from PowerPC code (timebase clock frequency).
117*4882a593Smuzhiyun * On ARM it returns the number of timer ticks per second.
118*4882a593Smuzhiyun */
get_tbclk(void)119*4882a593Smuzhiyun ulong get_tbclk(void)
120*4882a593Smuzhiyun {
121*4882a593Smuzhiyun return gpt_get_clk();
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun /*
125*4882a593Smuzhiyun * This function is intended for SHORT delays only.
126*4882a593Smuzhiyun * It will overflow at around 10 seconds @ 400MHz,
127*4882a593Smuzhiyun * or 20 seconds @ 200MHz.
128*4882a593Smuzhiyun */
usec2ticks(unsigned long _usec)129*4882a593Smuzhiyun unsigned long usec2ticks(unsigned long _usec)
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun unsigned long long usec = _usec;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun usec *= get_tbclk();
134*4882a593Smuzhiyun usec += 999999;
135*4882a593Smuzhiyun do_div(usec, 1000000);
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun return usec;
138*4882a593Smuzhiyun }
139