1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2011 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <asm/mach-imx/iomux-v3.h> 8*4882a593Smuzhiyun #include <asm/arch/iomux.h> 9*4882a593Smuzhiyun #include <asm/io.h> 10*4882a593Smuzhiyun #include <asm/arch/clock.h> 11*4882a593Smuzhiyun #include <asm/arch/sys_proto.h> 12*4882a593Smuzhiyun setup_sata(void)13*4882a593Smuzhiyunint setup_sata(void) 14*4882a593Smuzhiyun { 15*4882a593Smuzhiyun struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 16*4882a593Smuzhiyun int ret; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun if (!is_mx6dq() && !is_mx6dqp()) 19*4882a593Smuzhiyun return 1; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun ret = enable_sata_clock(); 22*4882a593Smuzhiyun if (ret) 23*4882a593Smuzhiyun return ret; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun clrsetbits_le32(&iomuxc_regs->gpr[13], 26*4882a593Smuzhiyun IOMUXC_GPR13_SATA_MASK, 27*4882a593Smuzhiyun IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB 28*4882a593Smuzhiyun |IOMUXC_GPR13_SATA_PHY_7_SATA2M 29*4882a593Smuzhiyun |IOMUXC_GPR13_SATA_SPEED_3G 30*4882a593Smuzhiyun |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT) 31*4882a593Smuzhiyun |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED 32*4882a593Smuzhiyun |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16 33*4882a593Smuzhiyun |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB 34*4882a593Smuzhiyun |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V 35*4882a593Smuzhiyun |IOMUXC_GPR13_SATA_PHY_1_SLOW); 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun return 0; 38*4882a593Smuzhiyun } 39