1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun * Copyright 2017 NXP
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <asm/io.h>
9*4882a593Smuzhiyun #include <asm/psci.h>
10*4882a593Smuzhiyun #include <asm/secure.h>
11*4882a593Smuzhiyun #include <asm/arch/imx-regs.h>
12*4882a593Smuzhiyun #include <common.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define GPC_CPU_PGC_SW_PDN_REQ 0xfc
16*4882a593Smuzhiyun #define GPC_CPU_PGC_SW_PUP_REQ 0xf0
17*4882a593Smuzhiyun #define GPC_PGC_C1 0x840
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7 0x2
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /* below is for i.MX7D */
22*4882a593Smuzhiyun #define SRC_GPR1_MX7D 0x074
23*4882a593Smuzhiyun #define SRC_A7RCR0 0x004
24*4882a593Smuzhiyun #define SRC_A7RCR1 0x008
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define BP_SRC_A7RCR0_A7_CORE_RESET0 0
27*4882a593Smuzhiyun #define BP_SRC_A7RCR1_A7_CORE1_ENABLE 1
28*4882a593Smuzhiyun
imx_gpcv2_set_m_core_pgc(bool enable,u32 offset)29*4882a593Smuzhiyun static inline void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun writel(enable, GPC_IPS_BASE_ADDR + offset);
32*4882a593Smuzhiyun }
33*4882a593Smuzhiyun
imx_gpcv2_set_core1_power(bool pdn)34*4882a593Smuzhiyun __secure void imx_gpcv2_set_core1_power(bool pdn)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun u32 reg = pdn ? GPC_CPU_PGC_SW_PUP_REQ : GPC_CPU_PGC_SW_PDN_REQ;
37*4882a593Smuzhiyun u32 val;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C1);
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun val = readl(GPC_IPS_BASE_ADDR + reg);
42*4882a593Smuzhiyun val |= BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7;
43*4882a593Smuzhiyun writel(val, GPC_IPS_BASE_ADDR + reg);
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun while ((readl(GPC_IPS_BASE_ADDR + reg) &
46*4882a593Smuzhiyun BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7) != 0)
47*4882a593Smuzhiyun ;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C1);
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
imx_enable_cpu_ca7(int cpu,bool enable)52*4882a593Smuzhiyun __secure void imx_enable_cpu_ca7(int cpu, bool enable)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun u32 mask, val;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun mask = 1 << (BP_SRC_A7RCR1_A7_CORE1_ENABLE + cpu - 1);
57*4882a593Smuzhiyun val = readl(SRC_BASE_ADDR + SRC_A7RCR1);
58*4882a593Smuzhiyun val = enable ? val | mask : val & ~mask;
59*4882a593Smuzhiyun writel(val, SRC_BASE_ADDR + SRC_A7RCR1);
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
imx_cpu_on(int fn,int cpu,int pc)62*4882a593Smuzhiyun __secure int imx_cpu_on(int fn, int cpu, int pc)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun writel(pc, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D);
65*4882a593Smuzhiyun imx_gpcv2_set_core1_power(true);
66*4882a593Smuzhiyun imx_enable_cpu_ca7(cpu, true);
67*4882a593Smuzhiyun return 0;
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
imx_cpu_off(int cpu)70*4882a593Smuzhiyun __secure int imx_cpu_off(int cpu)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun imx_enable_cpu_ca7(cpu, false);
73*4882a593Smuzhiyun imx_gpcv2_set_core1_power(false);
74*4882a593Smuzhiyun writel(0, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D + 4);
75*4882a593Smuzhiyun return 0;
76*4882a593Smuzhiyun }
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