1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2014
3*4882a593Smuzhiyun * Gabriel Huau <contact@huau-gabriel.fr>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * (C) Copyright 2009 Freescale Semiconductor, Inc.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <asm/io.h>
12*4882a593Smuzhiyun #include <linux/errno.h>
13*4882a593Smuzhiyun #include <asm/arch/sys_proto.h>
14*4882a593Smuzhiyun #include <asm/arch/imx-regs.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define MAX_CPUS 4
17*4882a593Smuzhiyun static struct src *src = (struct src *)SRC_BASE_ADDR;
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun static uint32_t cpu_reset_mask[MAX_CPUS] = {
20*4882a593Smuzhiyun 0, /* We don't really want to modify the cpu0 */
21*4882a593Smuzhiyun SRC_SCR_CORE_1_RESET_MASK,
22*4882a593Smuzhiyun SRC_SCR_CORE_2_RESET_MASK,
23*4882a593Smuzhiyun SRC_SCR_CORE_3_RESET_MASK
24*4882a593Smuzhiyun };
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun static uint32_t cpu_ctrl_mask[MAX_CPUS] = {
27*4882a593Smuzhiyun 0, /* We don't really want to modify the cpu0 */
28*4882a593Smuzhiyun SRC_SCR_CORE_1_ENABLE_MASK,
29*4882a593Smuzhiyun SRC_SCR_CORE_2_ENABLE_MASK,
30*4882a593Smuzhiyun SRC_SCR_CORE_3_ENABLE_MASK
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun
cpu_reset(int nr)33*4882a593Smuzhiyun int cpu_reset(int nr)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun /* Software reset of the CPU N */
36*4882a593Smuzhiyun src->scr |= cpu_reset_mask[nr];
37*4882a593Smuzhiyun return 0;
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun
cpu_status(int nr)40*4882a593Smuzhiyun int cpu_status(int nr)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun printf("core %d => %d\n", nr, !!(src->scr & cpu_ctrl_mask[nr]));
43*4882a593Smuzhiyun return 0;
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
cpu_release(int nr,int argc,char * const argv[])46*4882a593Smuzhiyun int cpu_release(int nr, int argc, char *const argv[])
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun uint32_t boot_addr;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun boot_addr = simple_strtoul(argv[0], NULL, 16);
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun switch (nr) {
53*4882a593Smuzhiyun case 1:
54*4882a593Smuzhiyun src->gpr3 = boot_addr;
55*4882a593Smuzhiyun break;
56*4882a593Smuzhiyun case 2:
57*4882a593Smuzhiyun src->gpr5 = boot_addr;
58*4882a593Smuzhiyun break;
59*4882a593Smuzhiyun case 3:
60*4882a593Smuzhiyun src->gpr7 = boot_addr;
61*4882a593Smuzhiyun break;
62*4882a593Smuzhiyun default:
63*4882a593Smuzhiyun return 1;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun /* CPU N is ready to start */
67*4882a593Smuzhiyun src->scr |= cpu_ctrl_mask[nr];
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun return 0;
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
is_core_valid(unsigned int core)72*4882a593Smuzhiyun int is_core_valid(unsigned int core)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun uint32_t nr_cores = get_nr_cpus();
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun if (core > nr_cores)
77*4882a593Smuzhiyun return 0;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun return 1;
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
cpu_disable(int nr)82*4882a593Smuzhiyun int cpu_disable(int nr)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun /* Disable the CPU N */
85*4882a593Smuzhiyun src->scr &= ~cpu_ctrl_mask[nr];
86*4882a593Smuzhiyun return 0;
87*4882a593Smuzhiyun }
88