1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2007
3*4882a593Smuzhiyun * Sascha Hauer, Pengutronix
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * (C) Copyright 2009 Freescale Semiconductor, Inc.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <asm/arch/imx-regs.h>
12*4882a593Smuzhiyun #include <asm/arch/clock.h>
13*4882a593Smuzhiyun #include <asm/arch/sys_proto.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <linux/errno.h>
16*4882a593Smuzhiyun #include <asm/io.h>
17*4882a593Smuzhiyun #include <asm/mach-imx/boot_mode.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #if !(defined(CONFIG_MX51) || defined(CONFIG_MX53))
20*4882a593Smuzhiyun #error "CPU_TYPE not defined"
21*4882a593Smuzhiyun #endif
22*4882a593Smuzhiyun
get_cpu_rev(void)23*4882a593Smuzhiyun u32 get_cpu_rev(void)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun #ifdef CONFIG_MX51
26*4882a593Smuzhiyun int system_rev = 0x51000;
27*4882a593Smuzhiyun #else
28*4882a593Smuzhiyun int system_rev = 0x53000;
29*4882a593Smuzhiyun #endif
30*4882a593Smuzhiyun int reg = __raw_readl(ROM_SI_REV);
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #if defined(CONFIG_MX51)
33*4882a593Smuzhiyun switch (reg) {
34*4882a593Smuzhiyun case 0x02:
35*4882a593Smuzhiyun system_rev |= CHIP_REV_1_1;
36*4882a593Smuzhiyun break;
37*4882a593Smuzhiyun case 0x10:
38*4882a593Smuzhiyun if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
39*4882a593Smuzhiyun system_rev |= CHIP_REV_2_5;
40*4882a593Smuzhiyun else
41*4882a593Smuzhiyun system_rev |= CHIP_REV_2_0;
42*4882a593Smuzhiyun break;
43*4882a593Smuzhiyun case 0x20:
44*4882a593Smuzhiyun system_rev |= CHIP_REV_3_0;
45*4882a593Smuzhiyun break;
46*4882a593Smuzhiyun default:
47*4882a593Smuzhiyun system_rev |= CHIP_REV_1_0;
48*4882a593Smuzhiyun break;
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun #else
51*4882a593Smuzhiyun if (reg < 0x20)
52*4882a593Smuzhiyun system_rev |= CHIP_REV_1_0;
53*4882a593Smuzhiyun else
54*4882a593Smuzhiyun system_rev |= reg;
55*4882a593Smuzhiyun #endif
56*4882a593Smuzhiyun return system_rev;
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun #ifdef CONFIG_REVISION_TAG
get_board_rev(void)60*4882a593Smuzhiyun u32 __weak get_board_rev(void)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun return get_cpu_rev();
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun #endif
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun #ifndef CONFIG_SYS_DCACHE_OFF
enable_caches(void)67*4882a593Smuzhiyun void enable_caches(void)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun /* Enable D-cache. I-cache is already enabled in start.S */
70*4882a593Smuzhiyun dcache_enable();
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun #endif
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun #if defined(CONFIG_FEC_MXC)
imx_get_mac_from_fuse(int dev_id,unsigned char * mac)75*4882a593Smuzhiyun void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun int i;
78*4882a593Smuzhiyun struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
79*4882a593Smuzhiyun struct fuse_bank *bank = &iim->bank[1];
80*4882a593Smuzhiyun struct fuse_bank1_regs *fuse =
81*4882a593Smuzhiyun (struct fuse_bank1_regs *)bank->fuse_regs;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun for (i = 0; i < 6; i++)
84*4882a593Smuzhiyun mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun #endif
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun #ifdef CONFIG_MX53
boot_mode_apply(unsigned cfg_val)89*4882a593Smuzhiyun void boot_mode_apply(unsigned cfg_val)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun writel(cfg_val, &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr);
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun /*
94*4882a593Smuzhiyun * cfg_val will be used for
95*4882a593Smuzhiyun * Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
96*4882a593Smuzhiyun *
97*4882a593Smuzhiyun * If bit 28 of LPGR is set upon watchdog reset,
98*4882a593Smuzhiyun * bits[25:0] of LPGR will move to SBMR.
99*4882a593Smuzhiyun */
100*4882a593Smuzhiyun const struct boot_mode soc_boot_modes[] = {
101*4882a593Smuzhiyun {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
102*4882a593Smuzhiyun /* usb or serial download */
103*4882a593Smuzhiyun {"usb", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x13)},
104*4882a593Smuzhiyun {"sata", MAKE_CFGVAL(0x28, 0x00, 0x00, 0x12)},
105*4882a593Smuzhiyun {"escpi1:0", MAKE_CFGVAL(0x38, 0x20, 0x00, 0x12)},
106*4882a593Smuzhiyun {"escpi1:1", MAKE_CFGVAL(0x38, 0x20, 0x04, 0x12)},
107*4882a593Smuzhiyun {"escpi1:2", MAKE_CFGVAL(0x38, 0x20, 0x08, 0x12)},
108*4882a593Smuzhiyun {"escpi1:3", MAKE_CFGVAL(0x38, 0x20, 0x0c, 0x12)},
109*4882a593Smuzhiyun /* 4 bit bus width */
110*4882a593Smuzhiyun {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
111*4882a593Smuzhiyun {"esdhc2", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
112*4882a593Smuzhiyun {"esdhc3", MAKE_CFGVAL(0x40, 0x20, 0x10, 0x12)},
113*4882a593Smuzhiyun {"esdhc4", MAKE_CFGVAL(0x40, 0x20, 0x18, 0x12)},
114*4882a593Smuzhiyun {NULL, 0},
115*4882a593Smuzhiyun };
116*4882a593Smuzhiyun #endif
117