1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2015 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <asm/io.h>
8*4882a593Smuzhiyun #include <asm/arch/imx-regs.h>
9*4882a593Smuzhiyun #include <asm/arch/clock.h>
10*4882a593Smuzhiyun #include <asm/arch/sys_proto.h>
11*4882a593Smuzhiyun #include <asm/mach-imx/boot_mode.h>
12*4882a593Smuzhiyun #include <asm/arch/crm_regs.h>
13*4882a593Smuzhiyun
init_aips(void)14*4882a593Smuzhiyun void init_aips(void)
15*4882a593Smuzhiyun {
16*4882a593Smuzhiyun struct aipstz_regs *aips1, *aips2, *aips3;
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
19*4882a593Smuzhiyun aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
20*4882a593Smuzhiyun aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /*
23*4882a593Smuzhiyun * Set all MPROTx to be non-bufferable, trusted for R/W,
24*4882a593Smuzhiyun * not forced to user-mode.
25*4882a593Smuzhiyun */
26*4882a593Smuzhiyun writel(0x77777777, &aips1->mprot0);
27*4882a593Smuzhiyun writel(0x77777777, &aips1->mprot1);
28*4882a593Smuzhiyun writel(0x77777777, &aips2->mprot0);
29*4882a593Smuzhiyun writel(0x77777777, &aips2->mprot1);
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /*
32*4882a593Smuzhiyun * Set all OPACRx to be non-bufferable, not require
33*4882a593Smuzhiyun * supervisor privilege level for access,allow for
34*4882a593Smuzhiyun * write access and untrusted master access.
35*4882a593Smuzhiyun */
36*4882a593Smuzhiyun writel(0x00000000, &aips1->opacr0);
37*4882a593Smuzhiyun writel(0x00000000, &aips1->opacr1);
38*4882a593Smuzhiyun writel(0x00000000, &aips1->opacr2);
39*4882a593Smuzhiyun writel(0x00000000, &aips1->opacr3);
40*4882a593Smuzhiyun writel(0x00000000, &aips1->opacr4);
41*4882a593Smuzhiyun writel(0x00000000, &aips2->opacr0);
42*4882a593Smuzhiyun writel(0x00000000, &aips2->opacr1);
43*4882a593Smuzhiyun writel(0x00000000, &aips2->opacr2);
44*4882a593Smuzhiyun writel(0x00000000, &aips2->opacr3);
45*4882a593Smuzhiyun writel(0x00000000, &aips2->opacr4);
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun if (is_mx6ull() || is_mx6sx() || is_mx7()) {
48*4882a593Smuzhiyun /*
49*4882a593Smuzhiyun * Set all MPROTx to be non-bufferable, trusted for R/W,
50*4882a593Smuzhiyun * not forced to user-mode.
51*4882a593Smuzhiyun */
52*4882a593Smuzhiyun writel(0x77777777, &aips3->mprot0);
53*4882a593Smuzhiyun writel(0x77777777, &aips3->mprot1);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /*
56*4882a593Smuzhiyun * Set all OPACRx to be non-bufferable, not require
57*4882a593Smuzhiyun * supervisor privilege level for access,allow for
58*4882a593Smuzhiyun * write access and untrusted master access.
59*4882a593Smuzhiyun */
60*4882a593Smuzhiyun writel(0x00000000, &aips3->opacr0);
61*4882a593Smuzhiyun writel(0x00000000, &aips3->opacr1);
62*4882a593Smuzhiyun writel(0x00000000, &aips3->opacr2);
63*4882a593Smuzhiyun writel(0x00000000, &aips3->opacr3);
64*4882a593Smuzhiyun writel(0x00000000, &aips3->opacr4);
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
imx_set_wdog_powerdown(bool enable)68*4882a593Smuzhiyun void imx_set_wdog_powerdown(bool enable)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
71*4882a593Smuzhiyun struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
72*4882a593Smuzhiyun struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
73*4882a593Smuzhiyun #ifdef CONFIG_MX7D
74*4882a593Smuzhiyun struct wdog_regs *wdog4 = (struct wdog_regs *)WDOG4_BASE_ADDR;
75*4882a593Smuzhiyun #endif
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun /* Write to the PDE (Power Down Enable) bit */
78*4882a593Smuzhiyun writew(enable, &wdog1->wmcr);
79*4882a593Smuzhiyun writew(enable, &wdog2->wmcr);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun if (is_mx6sx() || is_mx6ul() || is_mx7())
82*4882a593Smuzhiyun writew(enable, &wdog3->wmcr);
83*4882a593Smuzhiyun #ifdef CONFIG_MX7D
84*4882a593Smuzhiyun writew(enable, &wdog4->wmcr);
85*4882a593Smuzhiyun #endif
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun #define SRC_SCR_WARM_RESET_ENABLE 0
89*4882a593Smuzhiyun
init_src(void)90*4882a593Smuzhiyun void init_src(void)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun struct src *src_regs = (struct src *)SRC_BASE_ADDR;
93*4882a593Smuzhiyun u32 val;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun /*
96*4882a593Smuzhiyun * force warm reset sources to generate cold reset
97*4882a593Smuzhiyun * for a more reliable restart
98*4882a593Smuzhiyun */
99*4882a593Smuzhiyun val = readl(&src_regs->scr);
100*4882a593Smuzhiyun val &= ~(1 << SRC_SCR_WARM_RESET_ENABLE);
101*4882a593Smuzhiyun writel(val, &src_regs->scr);
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun #ifdef CONFIG_CMD_BMODE
boot_mode_apply(unsigned cfg_val)105*4882a593Smuzhiyun void boot_mode_apply(unsigned cfg_val)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun unsigned reg;
108*4882a593Smuzhiyun struct src *psrc = (struct src *)SRC_BASE_ADDR;
109*4882a593Smuzhiyun writel(cfg_val, &psrc->gpr9);
110*4882a593Smuzhiyun reg = readl(&psrc->gpr10);
111*4882a593Smuzhiyun if (cfg_val)
112*4882a593Smuzhiyun reg |= 1 << 28;
113*4882a593Smuzhiyun else
114*4882a593Smuzhiyun reg &= ~(1 << 28);
115*4882a593Smuzhiyun writel(reg, &psrc->gpr10);
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun #endif
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun #if defined(CONFIG_MX6)
imx6_src_get_boot_mode(void)120*4882a593Smuzhiyun u32 imx6_src_get_boot_mode(void)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun if (imx6_is_bmode_from_gpr9())
123*4882a593Smuzhiyun return readl(&src_base->gpr9);
124*4882a593Smuzhiyun else
125*4882a593Smuzhiyun return readl(&src_base->sbmr1);
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun #endif
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