1*4882a593Smuzhiyun /* Copyright (c) 2012 Samsung Electronics Co. Ltd 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Exynos Phy register definitions 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _ASM_ARCH_XHCI_EXYNOS_H_ 9*4882a593Smuzhiyun #define _ASM_ARCH_XHCI_EXYNOS_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* Phy register MACRO definitions */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define LINKSYSTEM_FLADJ_MASK (0x3f << 1) 14*4882a593Smuzhiyun #define LINKSYSTEM_FLADJ(_x) ((_x) << 1) 15*4882a593Smuzhiyun #define LINKSYSTEM_XHCI_VERSION_CONTROL (0x1 << 27) 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define PHYUTMI_OTGDISABLE (1 << 6) 18*4882a593Smuzhiyun #define PHYUTMI_FORCESUSPEND (1 << 1) 19*4882a593Smuzhiyun #define PHYUTMI_FORCESLEEP (1 << 0) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23) 22*4882a593Smuzhiyun #define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21) 25*4882a593Smuzhiyun #define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define PHYCLKRST_SSC_EN (0x1 << 20) 28*4882a593Smuzhiyun #define PHYCLKRST_REF_SSP_EN (0x1 << 19) 29*4882a593Smuzhiyun #define PHYCLKRST_REF_CLKDIV2 (0x1 << 18) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11) 32*4882a593Smuzhiyun #define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11) 33*4882a593Smuzhiyun #define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x02 << 11) 34*4882a593Smuzhiyun #define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11) 35*4882a593Smuzhiyun #define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11) 36*4882a593Smuzhiyun #define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define PHYCLKRST_FSEL_MASK (0x3f << 5) 39*4882a593Smuzhiyun #define PHYCLKRST_FSEL(_x) ((_x) << 5) 40*4882a593Smuzhiyun #define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5) 41*4882a593Smuzhiyun #define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5) 42*4882a593Smuzhiyun #define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5) 43*4882a593Smuzhiyun #define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define PHYCLKRST_RETENABLEN (0x1 << 4) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2) 48*4882a593Smuzhiyun #define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2) 49*4882a593Smuzhiyun #define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define PHYCLKRST_PORTRESET (0x1 << 1) 52*4882a593Smuzhiyun #define PHYCLKRST_COMMONONN (0x1 << 0) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define PHYPARAM0_REF_USE_PAD (0x1 << 31) 55*4882a593Smuzhiyun #define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26) 56*4882a593Smuzhiyun #define PHYPARAM0_REF_LOSLEVEL (0x9 << 26) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0) 59*4882a593Smuzhiyun #define PHYPARAM1_PCS_TXDEEMPH (0x1c) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define PHYTEST_POWERDOWN_SSP (0x1 << 3) 62*4882a593Smuzhiyun #define PHYTEST_POWERDOWN_HSP (0x1 << 2) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define PHYBATCHG_UTMI_CLKSEL (0x1 << 2) 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define FSEL_CLKSEL_24M (0x5) 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* XHCI PHY register structure */ 69*4882a593Smuzhiyun struct exynos_usb3_phy { 70*4882a593Smuzhiyun unsigned int reserve1; 71*4882a593Smuzhiyun unsigned int link_system; 72*4882a593Smuzhiyun unsigned int phy_utmi; 73*4882a593Smuzhiyun unsigned int phy_pipe; 74*4882a593Smuzhiyun unsigned int phy_clk_rst; 75*4882a593Smuzhiyun unsigned int phy_reg0; 76*4882a593Smuzhiyun unsigned int phy_reg1; 77*4882a593Smuzhiyun unsigned int phy_param0; 78*4882a593Smuzhiyun unsigned int phy_param1; 79*4882a593Smuzhiyun unsigned int phy_term; 80*4882a593Smuzhiyun unsigned int phy_test; 81*4882a593Smuzhiyun unsigned int phy_adp; 82*4882a593Smuzhiyun unsigned int phy_batchg; 83*4882a593Smuzhiyun unsigned int phy_resume; 84*4882a593Smuzhiyun unsigned int reserve2[3]; 85*4882a593Smuzhiyun unsigned int link_port; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #endif /* _ASM_ARCH_XHCI_EXYNOS_H_ */ 89