1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2011 Samsung Electronics 3*4882a593Smuzhiyun * Heungjun Kim <riverful.kim@samsung.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __ASM_ARM_ARCH_WATCHDOG_H_ 9*4882a593Smuzhiyun #define __ASM_ARM_ARCH_WATCHDOG_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define WTCON_RESET_OFFSET 0 12*4882a593Smuzhiyun #define WTCON_INTEN_OFFSET 2 13*4882a593Smuzhiyun #define WTCON_CLKSEL_OFFSET 3 14*4882a593Smuzhiyun #define WTCON_EN_OFFSET 5 15*4882a593Smuzhiyun #define WTCON_PRE_OFFSET 8 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define WTCON_CLK_16 0x0 18*4882a593Smuzhiyun #define WTCON_CLK_32 0x1 19*4882a593Smuzhiyun #define WTCON_CLK_64 0x2 20*4882a593Smuzhiyun #define WTCON_CLK_128 0x3 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define WTCON_CLK(x) ((x & 0x3) << WTCON_CLKSEL_OFFSET) 23*4882a593Smuzhiyun #define WTCON_PRESCALER(x) ((x) << WTCON_PRE_OFFSET) 24*4882a593Smuzhiyun #define WTCON_EN (0x1 << WTCON_EN_OFFSET) 25*4882a593Smuzhiyun #define WTCON_RESET (0x1 << WTCON_RESET_OFFSET) 26*4882a593Smuzhiyun #define WTCON_INT (0x1 << WTCON_INTEN_OFFSET) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 29*4882a593Smuzhiyun struct s5p_watchdog { 30*4882a593Smuzhiyun unsigned int wtcon; 31*4882a593Smuzhiyun unsigned int wtdat; 32*4882a593Smuzhiyun unsigned int wtcnt; 33*4882a593Smuzhiyun unsigned int wtclrint; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* functions */ 37*4882a593Smuzhiyun void wdt_stop(void); 38*4882a593Smuzhiyun void wdt_start(unsigned int timeout); 39*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #endif 42