1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2012 Samsung Electronics Co., Ltd. 3*4882a593Smuzhiyun * http://www.samsung.com 4*4882a593Smuzhiyun * Akshay Saraswat <akshay.s@samsung.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * EXYNOS - Thermal Management Unit 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * See file CREDITS for list of people who contributed to this 9*4882a593Smuzhiyun * project. 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 12*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as 13*4882a593Smuzhiyun * published by the Free Software Foundation. 14*4882a593Smuzhiyun * You should have received a copy of the GNU General Public License 15*4882a593Smuzhiyun * along with this program; if not, write to the Free Software 16*4882a593Smuzhiyun * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17*4882a593Smuzhiyun * MA 02111-1307 USA 18*4882a593Smuzhiyun */ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #ifndef __ASM_ARCH_TMU_H 21*4882a593Smuzhiyun #define __ASM_ARCH_TMU_H 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun struct exynos5_tmu_reg { 24*4882a593Smuzhiyun u32 triminfo; 25*4882a593Smuzhiyun u32 rsvd1[4]; 26*4882a593Smuzhiyun u32 triminfo_control; 27*4882a593Smuzhiyun u32 rsvd5[2]; 28*4882a593Smuzhiyun u32 tmu_control; 29*4882a593Smuzhiyun u32 rsvd7; 30*4882a593Smuzhiyun u32 tmu_status; 31*4882a593Smuzhiyun u32 sampling_internal; 32*4882a593Smuzhiyun u32 counter_value0; 33*4882a593Smuzhiyun u32 counter_value1; 34*4882a593Smuzhiyun u32 rsvd8[2]; 35*4882a593Smuzhiyun u32 current_temp; 36*4882a593Smuzhiyun u32 rsvd10[3]; 37*4882a593Smuzhiyun u32 threshold_temp_rise; 38*4882a593Smuzhiyun u32 threshold_temp_fall; 39*4882a593Smuzhiyun u32 rsvd13[2]; 40*4882a593Smuzhiyun u32 past_temp3_0; 41*4882a593Smuzhiyun u32 past_temp7_4; 42*4882a593Smuzhiyun u32 past_temp11_8; 43*4882a593Smuzhiyun u32 past_temp15_12; 44*4882a593Smuzhiyun u32 inten; 45*4882a593Smuzhiyun u32 intstat; 46*4882a593Smuzhiyun u32 intclear; 47*4882a593Smuzhiyun u32 rsvd15; 48*4882a593Smuzhiyun u32 emul_con; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun #endif /* __ASM_ARCH_TMU_H */ 51