1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2012 Samsung Electronics 3*4882a593Smuzhiyun * Donghwa Lee <dh09.lee@samsung.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __ASM_ARM_ARCH_SYSTEM_H_ 9*4882a593Smuzhiyun #define __ASM_ARM_ARCH_SYSTEM_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 12*4882a593Smuzhiyun struct exynos4_sysreg { 13*4882a593Smuzhiyun unsigned char res1[0x210]; 14*4882a593Smuzhiyun unsigned int display_ctrl; 15*4882a593Smuzhiyun unsigned int display_ctrl2; 16*4882a593Smuzhiyun unsigned int camera_control; 17*4882a593Smuzhiyun unsigned int audio_endian; 18*4882a593Smuzhiyun unsigned int jtag_con; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun struct exynos5_sysreg { 22*4882a593Smuzhiyun unsigned char res1[0x214]; 23*4882a593Smuzhiyun unsigned int disp1blk_cfg; 24*4882a593Smuzhiyun unsigned int disp2blk_cfg; 25*4882a593Smuzhiyun unsigned int hdcp_e_fuse; 26*4882a593Smuzhiyun unsigned int gsclblk_cfg0; 27*4882a593Smuzhiyun unsigned int gsclblk_cfg1; 28*4882a593Smuzhiyun unsigned int reserved; 29*4882a593Smuzhiyun unsigned int ispblk_cfg; 30*4882a593Smuzhiyun unsigned int usb20phy_cfg; 31*4882a593Smuzhiyun unsigned char res2[0x29c]; 32*4882a593Smuzhiyun unsigned int mipi_dphy; 33*4882a593Smuzhiyun unsigned int dptx_dphy; 34*4882a593Smuzhiyun unsigned int phyclk_sel; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun #endif 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define USB20_PHY_CFG_HOST_LINK_EN (1 << 0) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* 41*4882a593Smuzhiyun * This instruction causes an event to be signaled to all cores 42*4882a593Smuzhiyun * within a multiprocessor system. If SEV is implemented, 43*4882a593Smuzhiyun * WFE must also be implemented. 44*4882a593Smuzhiyun */ 45*4882a593Smuzhiyun #define sev() __asm__ __volatile__ ("sev\n\t" : : ); 46*4882a593Smuzhiyun /* 47*4882a593Smuzhiyun * If the Event Register is not set, WFE suspends execution until 48*4882a593Smuzhiyun * one of the following events occurs: 49*4882a593Smuzhiyun * - an IRQ interrupt, unless masked by the CPSR I-bit 50*4882a593Smuzhiyun * - an FIQ interrupt, unless masked by the CPSR F-bit 51*4882a593Smuzhiyun * - an Imprecise Data abort, unless masked by the CPSR A-bit 52*4882a593Smuzhiyun * - a Debug Entry request, if Debug is enabled 53*4882a593Smuzhiyun * - an Event signaled by another processor using the SEV instruction. 54*4882a593Smuzhiyun * If the Event Register is set, WFE clears it and returns immediately. 55*4882a593Smuzhiyun * If WFE is implemented, SEV must also be implemented. 56*4882a593Smuzhiyun */ 57*4882a593Smuzhiyun #define wfe() __asm__ __volatile__ ("wfe\n\t" : : ); 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* Move 0xd3 value to CPSR register to enable SVC mode */ 60*4882a593Smuzhiyun #define svc32_mode_en() __asm__ __volatile__ \ 61*4882a593Smuzhiyun ("@ I&F disable, Mode: 0x13 - SVC\n\t" \ 62*4882a593Smuzhiyun "msr cpsr_c, #0x13|0xC0\n\t" : : ) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* Set program counter with the given value */ 65*4882a593Smuzhiyun #define set_pc(x) __asm__ __volatile__ ("mov pc, %0\n\t" : : "r"(x)) 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* Branch to the given location */ 68*4882a593Smuzhiyun #define branch_bx(x) __asm__ __volatile__ ("bx %0\n\t" : : "r"(x)) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* Read Main Id register */ 71*4882a593Smuzhiyun #define mrc_midr(x) __asm__ __volatile__ \ 72*4882a593Smuzhiyun ("mrc p15, 0, %0, c0, c0, 0\n\t" : "=r"(x) : ) 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* Read Multiprocessor Affinity Register */ 75*4882a593Smuzhiyun #define mrc_mpafr(x) __asm__ __volatile__ \ 76*4882a593Smuzhiyun ("mrc p15, 0, %0, c0, c0, 5\n\t" : "=r"(x) : ) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* Read System Control Register */ 79*4882a593Smuzhiyun #define mrc_sctlr(x) __asm__ __volatile__ \ 80*4882a593Smuzhiyun ("mrc p15, 0, %0, c1, c0, 0\n\t" : "=r"(x) : ) 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* Read Auxiliary Control Register */ 83*4882a593Smuzhiyun #define mrc_auxr(x) __asm__ __volatile__ \ 84*4882a593Smuzhiyun ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(x) : ) 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* Read L2 Control register */ 87*4882a593Smuzhiyun #define mrc_l2_ctlr(x) __asm__ __volatile__ \ 88*4882a593Smuzhiyun ("mrc p15, 1, %0, c9, c0, 2\n\t" : "=r"(x) : ) 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* Read L2 Auxilliary Control register */ 91*4882a593Smuzhiyun #define mrc_l2_aux_ctlr(x) __asm__ __volatile__ \ 92*4882a593Smuzhiyun ("mrc p15, 1, %0, c15, c0, 0\n\t" : "=r"(x) : ) 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* Write System Control Register */ 95*4882a593Smuzhiyun #define mcr_sctlr(x) __asm__ __volatile__ \ 96*4882a593Smuzhiyun ("mcr p15, 0, %0, c1, c0, 0\n\t" : : "r"(x)) 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* Write Auxiliary Control Register */ 99*4882a593Smuzhiyun #define mcr_auxr(x) __asm__ __volatile__ \ 100*4882a593Smuzhiyun ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(x)) 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* Invalidate all instruction caches to PoU */ 103*4882a593Smuzhiyun #define mcr_icache(x) __asm__ __volatile__ \ 104*4882a593Smuzhiyun ("mcr p15, 0, %0, c7, c5, 0\n\t" : : "r"(x)) 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* Invalidate unified TLB */ 107*4882a593Smuzhiyun #define mcr_tlb(x) __asm__ __volatile__ \ 108*4882a593Smuzhiyun ("mcr p15, 0, %0, c8, c7, 0\n\t" : : "r"(x)) 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* Write L2 Control register */ 111*4882a593Smuzhiyun #define mcr_l2_ctlr(x) __asm__ __volatile__ \ 112*4882a593Smuzhiyun ("mcr p15, 1, %0, c9, c0, 2\n\t" : : "r"(x)) 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun /* Write L2 Auxilliary Control register */ 115*4882a593Smuzhiyun #define mcr_l2_aux_ctlr(x) __asm__ __volatile__ \ 116*4882a593Smuzhiyun ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(x)) 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun void set_usbhost_mode(unsigned int mode); 119*4882a593Smuzhiyun void set_system_display_ctrl(void); 120*4882a593Smuzhiyun int exynos_lcd_early_init(const void *blob); 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun #endif /* _EXYNOS4_SYSTEM_H */ 123