1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2012 SAMSUNG Electronics 3*4882a593Smuzhiyun * Padmavathi Venna <padma.v@samsung.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __ASM_ARCH_EXYNOS_COMMON_SPI_H_ 9*4882a593Smuzhiyun #define __ASM_ARCH_EXYNOS_COMMON_SPI_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* SPI peripheral register map; padded to 64KB */ 14*4882a593Smuzhiyun struct exynos_spi { 15*4882a593Smuzhiyun unsigned int ch_cfg; /* 0x00 */ 16*4882a593Smuzhiyun unsigned char reserved0[4]; 17*4882a593Smuzhiyun unsigned int mode_cfg; /* 0x08 */ 18*4882a593Smuzhiyun unsigned int cs_reg; /* 0x0c */ 19*4882a593Smuzhiyun unsigned char reserved1[4]; 20*4882a593Smuzhiyun unsigned int spi_sts; /* 0x14 */ 21*4882a593Smuzhiyun unsigned int tx_data; /* 0x18 */ 22*4882a593Smuzhiyun unsigned int rx_data; /* 0x1c */ 23*4882a593Smuzhiyun unsigned int pkt_cnt; /* 0x20 */ 24*4882a593Smuzhiyun unsigned char reserved2[4]; 25*4882a593Smuzhiyun unsigned int swap_cfg; /* 0x28 */ 26*4882a593Smuzhiyun unsigned int fb_clk; /* 0x2c */ 27*4882a593Smuzhiyun unsigned char padding[0xffd0]; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define EXYNOS_SPI_MAX_FREQ 50000000 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define SPI_TIMEOUT_MS 10 33*4882a593Smuzhiyun #define SF_READ_DATA_CMD 0x3 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* SPI_CHCFG */ 36*4882a593Smuzhiyun #define SPI_CH_HS_EN (1 << 6) 37*4882a593Smuzhiyun #define SPI_CH_RST (1 << 5) 38*4882a593Smuzhiyun #define SPI_SLAVE_MODE (1 << 4) 39*4882a593Smuzhiyun #define SPI_CH_CPOL_L (1 << 3) 40*4882a593Smuzhiyun #define SPI_CH_CPHA_B (1 << 2) 41*4882a593Smuzhiyun #define SPI_RX_CH_ON (1 << 1) 42*4882a593Smuzhiyun #define SPI_TX_CH_ON (1 << 0) 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* SPI_MODECFG */ 45*4882a593Smuzhiyun #define SPI_MODE_CH_WIDTH_WORD (0x2 << 29) 46*4882a593Smuzhiyun #define SPI_MODE_BUS_WIDTH_WORD (0x2 << 17) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* SPI_CSREG */ 49*4882a593Smuzhiyun #define SPI_SLAVE_SIG_INACT (1 << 0) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* SPI_STS */ 52*4882a593Smuzhiyun #define SPI_ST_TX_DONE (1 << 25) 53*4882a593Smuzhiyun #define SPI_FIFO_LVL_MASK 0x1ff 54*4882a593Smuzhiyun #define SPI_TX_LVL_OFFSET 6 55*4882a593Smuzhiyun #define SPI_RX_LVL_OFFSET 15 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* Feedback Delay */ 58*4882a593Smuzhiyun #define SPI_CLK_BYPASS (0 << 0) 59*4882a593Smuzhiyun #define SPI_FB_DELAY_90 (1 << 0) 60*4882a593Smuzhiyun #define SPI_FB_DELAY_180 (2 << 0) 61*4882a593Smuzhiyun #define SPI_FB_DELAY_270 (3 << 0) 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* Packet Count */ 64*4882a593Smuzhiyun #define SPI_PACKET_CNT_EN (1 << 16) 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* Swap config */ 67*4882a593Smuzhiyun #define SPI_TX_SWAP_EN (1 << 0) 68*4882a593Smuzhiyun #define SPI_TX_BYTE_SWAP (1 << 2) 69*4882a593Smuzhiyun #define SPI_TX_HWORD_SWAP (1 << 3) 70*4882a593Smuzhiyun #define SPI_TX_BYTE_SWAP (1 << 2) 71*4882a593Smuzhiyun #define SPI_RX_SWAP_EN (1 << 4) 72*4882a593Smuzhiyun #define SPI_RX_BYTE_SWAP (1 << 6) 73*4882a593Smuzhiyun #define SPI_RX_HWORD_SWAP (1 << 7) 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 76*4882a593Smuzhiyun #endif 77