1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2012 Samsung Electronics 3*4882a593Smuzhiyun * Rajeshwari Shinde <rajeshwari.s@samsung.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __ASM_ARM_ARCH_PERIPH_H 9*4882a593Smuzhiyun #define __ASM_ARM_ARCH_PERIPH_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * Peripherals required for pinmux configuration. List will 13*4882a593Smuzhiyun * grow with support for more devices getting added. 14*4882a593Smuzhiyun * Numbering based on interrupt table. 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun enum periph_id { 18*4882a593Smuzhiyun PERIPH_ID_UART0 = 51, 19*4882a593Smuzhiyun PERIPH_ID_UART1, 20*4882a593Smuzhiyun PERIPH_ID_UART2, 21*4882a593Smuzhiyun PERIPH_ID_UART3, 22*4882a593Smuzhiyun PERIPH_ID_I2C0 = 56, 23*4882a593Smuzhiyun PERIPH_ID_I2C1, 24*4882a593Smuzhiyun PERIPH_ID_I2C2, 25*4882a593Smuzhiyun PERIPH_ID_I2C3, 26*4882a593Smuzhiyun PERIPH_ID_I2C4, 27*4882a593Smuzhiyun PERIPH_ID_I2C5, 28*4882a593Smuzhiyun PERIPH_ID_I2C6, 29*4882a593Smuzhiyun PERIPH_ID_I2C7, 30*4882a593Smuzhiyun PERIPH_ID_SPI0 = 68, 31*4882a593Smuzhiyun PERIPH_ID_SPI1, 32*4882a593Smuzhiyun PERIPH_ID_SPI2, 33*4882a593Smuzhiyun PERIPH_ID_SDMMC0 = 75, 34*4882a593Smuzhiyun PERIPH_ID_SDMMC1, 35*4882a593Smuzhiyun PERIPH_ID_SDMMC2, 36*4882a593Smuzhiyun PERIPH_ID_SDMMC3, 37*4882a593Smuzhiyun PERIPH_ID_I2C8 = 87, 38*4882a593Smuzhiyun PERIPH_ID_I2C9, 39*4882a593Smuzhiyun PERIPH_ID_I2S0 = 98, 40*4882a593Smuzhiyun PERIPH_ID_I2S1 = 99, 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* Since following peripherals do 43*4882a593Smuzhiyun * not have shared peripheral interrupts (SPIs) 44*4882a593Smuzhiyun * they are numbered arbitiraly after the maximum 45*4882a593Smuzhiyun * SPIs Exynos has (128) 46*4882a593Smuzhiyun */ 47*4882a593Smuzhiyun PERIPH_ID_SROMC = 128, 48*4882a593Smuzhiyun PERIPH_ID_SPI3, 49*4882a593Smuzhiyun PERIPH_ID_SPI4, 50*4882a593Smuzhiyun PERIPH_ID_SDMMC4, 51*4882a593Smuzhiyun PERIPH_ID_PWM0, 52*4882a593Smuzhiyun PERIPH_ID_PWM1, 53*4882a593Smuzhiyun PERIPH_ID_PWM2, 54*4882a593Smuzhiyun PERIPH_ID_PWM3, 55*4882a593Smuzhiyun PERIPH_ID_PWM4, 56*4882a593Smuzhiyun PERIPH_ID_DPHPD, 57*4882a593Smuzhiyun PERIPH_ID_I2C10 = 203, 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun PERIPH_ID_NONE = -1, 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #endif /* __ASM_ARM_ARCH_PERIPH_H */ 63