1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2009 SAMSUNG Electronics 3*4882a593Smuzhiyun * Minkyu Kang <mk7.kang@samsung.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __ASM_ARCH_MMC_H_ 9*4882a593Smuzhiyun #define __ASM_ARCH_MMC_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define S5P_MMC_DEV_OFFSET 0x10000 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define SDHCI_CONTROL2 0x80 14*4882a593Smuzhiyun #define SDHCI_CONTROL3 0x84 15*4882a593Smuzhiyun #define SDHCI_CONTROL4 0x8C 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define SDHCI_CTRL2_ENSTAASYNCCLR (1 << 31) 18*4882a593Smuzhiyun #define SDHCI_CTRL2_ENCMDCNFMSK (1 << 30) 19*4882a593Smuzhiyun #define SDHCI_CTRL2_CDINVRXD3 (1 << 29) 20*4882a593Smuzhiyun #define SDHCI_CTRL2_SLCARDOUT (1 << 28) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24) 23*4882a593Smuzhiyun #define SDHCI_CTRL2_FLTCLKSEL_SHIFT (24) 24*4882a593Smuzhiyun #define SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define SDHCI_CTRL2_LVLDAT_MASK (0xff << 16) 27*4882a593Smuzhiyun #define SDHCI_CTRL2_LVLDAT_SHIFT (16) 28*4882a593Smuzhiyun #define SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define SDHCI_CTRL2_ENFBCLKTX (1 << 15) 31*4882a593Smuzhiyun #define SDHCI_CTRL2_ENFBCLKRX (1 << 14) 32*4882a593Smuzhiyun #define SDHCI_CTRL2_SDCDSEL (1 << 13) 33*4882a593Smuzhiyun #define SDHCI_CTRL2_SDSIGPC (1 << 12) 34*4882a593Smuzhiyun #define SDHCI_CTRL2_ENBUSYCHKTXSTART (1 << 11) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define SDHCI_CTRL2_DFCNT_MASK(_x) ((_x) << 9) 37*4882a593Smuzhiyun #define SDHCI_CTRL2_DFCNT_SHIFT (9) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define SDHCI_CTRL2_ENCLKOUTHOLD (1 << 8) 40*4882a593Smuzhiyun #define SDHCI_CTRL2_RWAITMODE (1 << 7) 41*4882a593Smuzhiyun #define SDHCI_CTRL2_DISBUFRD (1 << 6) 42*4882a593Smuzhiyun #define SDHCI_CTRL2_SELBASECLK_MASK(_x) ((_x) << 4) 43*4882a593Smuzhiyun #define SDHCI_CTRL2_SELBASECLK_SHIFT (4) 44*4882a593Smuzhiyun #define SDHCI_CTRL2_PWRSYNC (1 << 3) 45*4882a593Smuzhiyun #define SDHCI_CTRL2_ENCLKOUTMSKCON (1 << 1) 46*4882a593Smuzhiyun #define SDHCI_CTRL2_HWINITFIN (1 << 0) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define SDHCI_CTRL3_FCSEL3 (1 << 31) 49*4882a593Smuzhiyun #define SDHCI_CTRL3_FCSEL2 (1 << 23) 50*4882a593Smuzhiyun #define SDHCI_CTRL3_FCSEL1 (1 << 15) 51*4882a593Smuzhiyun #define SDHCI_CTRL3_FCSEL0 (1 << 7) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define SDHCI_CTRL4_DRIVE_MASK(_x) ((_x) << 16) 54*4882a593Smuzhiyun #define SDHCI_CTRL4_DRIVE_SHIFT (16) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define SDHCI_MAX_HOSTS 4 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun int s5p_sdhci_init(u32 regbase, int index, int bus_width); 59*4882a593Smuzhiyun s5p_mmc_init(int index,int bus_width)60*4882a593Smuzhiyunstatic inline int s5p_mmc_init(int index, int bus_width) 61*4882a593Smuzhiyun { 62*4882a593Smuzhiyun unsigned int base = samsung_get_base_mmc() + 63*4882a593Smuzhiyun (S5P_MMC_DEV_OFFSET * index); 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun return s5p_sdhci_init(base, index, bus_width); 66*4882a593Smuzhiyun } 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun int exynos_mmc_init(const void *blob); 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #endif 71