1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2012 Samsung Electronics 3*4882a593Smuzhiyun * R. Chandrasekar <rcsekar@samsung.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __I2S_REGS_H__ 9*4882a593Smuzhiyun #define __I2S_REGS_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define CON_RESET (1 << 31) 12*4882a593Smuzhiyun #define CON_TXFIFO_FULL (1 << 8) 13*4882a593Smuzhiyun #define CON_TXCH_PAUSE (1 << 4) 14*4882a593Smuzhiyun #define CON_ACTIVE (1 << 0) 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define MOD_OP_CLK (3 << 30) 17*4882a593Smuzhiyun #define MOD_BLCP_SHIFT 24 18*4882a593Smuzhiyun #define MOD_BLCP_16BIT (0 << MOD_BLCP_SHIFT) 19*4882a593Smuzhiyun #define MOD_BLCP_8BIT (1 << MOD_BLCP_SHIFT) 20*4882a593Smuzhiyun #define MOD_BLCP_24BIT (2 << MOD_BLCP_SHIFT) 21*4882a593Smuzhiyun #define MOD_BLCP_MASK (3 << MOD_BLCP_SHIFT) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define MOD_BLC_16BIT (0 << 13) 24*4882a593Smuzhiyun #define MOD_BLC_8BIT (1 << 13) 25*4882a593Smuzhiyun #define MOD_BLC_24BIT (2 << 13) 26*4882a593Smuzhiyun #define MOD_BLC_MASK (3 << 13) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define MOD_SLAVE (1 << 11) 29*4882a593Smuzhiyun #define MOD_RCLKSRC (0 << 10) 30*4882a593Smuzhiyun #define MOD_MASK (3 << 8) 31*4882a593Smuzhiyun #define MOD_LR_LLOW (0 << 7) 32*4882a593Smuzhiyun #define MOD_LR_RLOW (1 << 7) 33*4882a593Smuzhiyun #define MOD_SDF_IIS (0 << 5) 34*4882a593Smuzhiyun #define MOD_SDF_MSB (1 << 5) 35*4882a593Smuzhiyun #define MOD_SDF_LSB (2 << 5) 36*4882a593Smuzhiyun #define MOD_SDF_MASK (3 << 5) 37*4882a593Smuzhiyun #define MOD_RCLK_256FS (0 << 3) 38*4882a593Smuzhiyun #define MOD_RCLK_512FS (1 << 3) 39*4882a593Smuzhiyun #define MOD_RCLK_384FS (2 << 3) 40*4882a593Smuzhiyun #define MOD_RCLK_768FS (3 << 3) 41*4882a593Smuzhiyun #define MOD_RCLK_MASK (3 << 3) 42*4882a593Smuzhiyun #define MOD_BCLK_32FS (0 << 1) 43*4882a593Smuzhiyun #define MOD_BCLK_48FS (1 << 1) 44*4882a593Smuzhiyun #define MOD_BCLK_16FS (2 << 1) 45*4882a593Smuzhiyun #define MOD_BCLK_24FS (3 << 1) 46*4882a593Smuzhiyun #define MOD_BCLK_MASK (3 << 1) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define MOD_CDCLKCON (1 << 12) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define FIC_TXFLUSH (1 << 15) 51*4882a593Smuzhiyun #define FIC_RXFLUSH (1 << 7) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define PSREN (1 << 15) 54*4882a593Smuzhiyun #define PSVAL (3 << 8) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #endif /* __I2S_REGS_H__ */ 57