1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * SAMSUNG EXYNOS USB HOST EHCI Controller 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2012 Samsung Electronics Co.Ltd 5*4882a593Smuzhiyun * Vivek Gautam <gautam.vivek@samsung.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __ASM_ARM_ARCH_EHCI_H__ 11*4882a593Smuzhiyun #define __ASM_ARM_ARCH_EHCI_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define CLK_24MHZ 5 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define PHYPWR_NORMAL_MASK_PHY0 (0x39 << 0) 16*4882a593Smuzhiyun #define PHYPWR_NORMAL_MASK_PHY1 (0x7 << 6) 17*4882a593Smuzhiyun #define PHYPWR_NORMAL_MASK_HSIC0 (0x7 << 9) 18*4882a593Smuzhiyun #define PHYPWR_NORMAL_MASK_HSIC1 (0x7 << 12) 19*4882a593Smuzhiyun #define RSTCON_HOSTPHY_SWRST (0xf << 3) 20*4882a593Smuzhiyun #define RSTCON_SWRST (0x1 << 0) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define HOST_CTRL0_PHYSWRSTALL (1 << 31) 23*4882a593Smuzhiyun #define HOST_CTRL0_COMMONON_N (1 << 9) 24*4882a593Smuzhiyun #define HOST_CTRL0_SIDDQ (1 << 6) 25*4882a593Smuzhiyun #define HOST_CTRL0_FORCESLEEP (1 << 5) 26*4882a593Smuzhiyun #define HOST_CTRL0_FORCESUSPEND (1 << 4) 27*4882a593Smuzhiyun #define HOST_CTRL0_WORDINTERFACE (1 << 3) 28*4882a593Smuzhiyun #define HOST_CTRL0_UTMISWRST (1 << 2) 29*4882a593Smuzhiyun #define HOST_CTRL0_LINKSWRST (1 << 1) 30*4882a593Smuzhiyun #define HOST_CTRL0_PHYSWRST (1 << 0) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define HOST_CTRL0_FSEL_MASK (7 << 16) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define EHCICTRL_ENAINCRXALIGN (1 << 29) 35*4882a593Smuzhiyun #define EHCICTRL_ENAINCR4 (1 << 28) 36*4882a593Smuzhiyun #define EHCICTRL_ENAINCR8 (1 << 27) 37*4882a593Smuzhiyun #define EHCICTRL_ENAINCR16 (1 << 26) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define HSIC_CTRL_REFCLKSEL (0x2) 40*4882a593Smuzhiyun #define HSIC_CTRL_REFCLKSEL_MASK (0x3) 41*4882a593Smuzhiyun #define HSIC_CTRL_REFCLKSEL_SHIFT (23) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define HSIC_CTRL_REFCLKDIV_12 (0x24) 44*4882a593Smuzhiyun #define HSIC_CTRL_REFCLKDIV_MASK (0x7f) 45*4882a593Smuzhiyun #define HSIC_CTRL_REFCLKDIV_SHIFT (16) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define HSIC_CTRL_SIDDQ (0x1 << 6) 48*4882a593Smuzhiyun #define HSIC_CTRL_FORCESLEEP (0x1 << 5) 49*4882a593Smuzhiyun #define HSIC_CTRL_FORCESUSPEND (0x1 << 4) 50*4882a593Smuzhiyun #define HSIC_CTRL_UTMISWRST (0x1 << 2) 51*4882a593Smuzhiyun #define HSIC_CTRL_PHYSWRST (0x1 << 0) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* Register map for PHY control */ 54*4882a593Smuzhiyun struct exynos_usb_phy { 55*4882a593Smuzhiyun unsigned int usbphyctrl0; 56*4882a593Smuzhiyun unsigned int usbphytune0; 57*4882a593Smuzhiyun unsigned int reserved1[2]; 58*4882a593Smuzhiyun unsigned int hsicphyctrl1; 59*4882a593Smuzhiyun unsigned int hsicphytune1; 60*4882a593Smuzhiyun unsigned int reserved2[2]; 61*4882a593Smuzhiyun unsigned int hsicphyctrl2; 62*4882a593Smuzhiyun unsigned int hsicphytune2; 63*4882a593Smuzhiyun unsigned int reserved3[2]; 64*4882a593Smuzhiyun unsigned int ehcictrl; 65*4882a593Smuzhiyun unsigned int ohcictrl; 66*4882a593Smuzhiyun unsigned int usbotgsys; 67*4882a593Smuzhiyun unsigned int reserved4; 68*4882a593Smuzhiyun unsigned int usbotgtune; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun struct exynos4412_usb_phy { 72*4882a593Smuzhiyun unsigned int usbphyctrl; 73*4882a593Smuzhiyun unsigned int usbphyclk; 74*4882a593Smuzhiyun unsigned int usbphyrstcon; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* Switch on the VBUS power. */ 78*4882a593Smuzhiyun int board_usb_vbus_init(void); 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #endif /* __ASM_ARM_ARCH_EHCI_H__ */ 81