1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2012 Samsung Electronics
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Author: Donghwa Lee <dh09.lee@samsung.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #ifndef _DP_INFO_H
10*4882a593Smuzhiyun #define _DP_INFO_H
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #define msleep(a) udelay(a * 1000)
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #define DP_TIMEOUT_LOOP_COUNT 100
15*4882a593Smuzhiyun #define MAX_CR_LOOP 5
16*4882a593Smuzhiyun #define MAX_EQ_LOOP 4
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define EXYNOS_DP_SUCCESS 0
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun enum {
21*4882a593Smuzhiyun DP_DISABLE,
22*4882a593Smuzhiyun DP_ENABLE,
23*4882a593Smuzhiyun };
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun struct edp_disp_info {
26*4882a593Smuzhiyun char *name;
27*4882a593Smuzhiyun unsigned int h_total;
28*4882a593Smuzhiyun unsigned int h_res;
29*4882a593Smuzhiyun unsigned int h_sync_width;
30*4882a593Smuzhiyun unsigned int h_back_porch;
31*4882a593Smuzhiyun unsigned int h_front_porch;
32*4882a593Smuzhiyun unsigned int v_total;
33*4882a593Smuzhiyun unsigned int v_res;
34*4882a593Smuzhiyun unsigned int v_sync_width;
35*4882a593Smuzhiyun unsigned int v_back_porch;
36*4882a593Smuzhiyun unsigned int v_front_porch;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun unsigned int v_sync_rate;
39*4882a593Smuzhiyun };
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun struct edp_link_train_info {
42*4882a593Smuzhiyun unsigned int lt_status;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun unsigned int ep_loop;
45*4882a593Smuzhiyun unsigned int cr_loop[4];
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun struct edp_video_info {
50*4882a593Smuzhiyun unsigned int master_mode;
51*4882a593Smuzhiyun unsigned int bist_mode;
52*4882a593Smuzhiyun unsigned int bist_pattern;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun unsigned int h_sync_polarity;
55*4882a593Smuzhiyun unsigned int v_sync_polarity;
56*4882a593Smuzhiyun unsigned int interlaced;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun unsigned int color_space;
59*4882a593Smuzhiyun unsigned int dynamic_range;
60*4882a593Smuzhiyun unsigned int ycbcr_coeff;
61*4882a593Smuzhiyun unsigned int color_depth;
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun struct exynos_dp_priv {
65*4882a593Smuzhiyun struct edp_disp_info disp_info;
66*4882a593Smuzhiyun struct edp_link_train_info lt_info;
67*4882a593Smuzhiyun struct edp_video_info video_info;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /*below info get from panel during training*/
70*4882a593Smuzhiyun unsigned char lane_bw;
71*4882a593Smuzhiyun unsigned char lane_cnt;
72*4882a593Smuzhiyun unsigned char dpcd_rev;
73*4882a593Smuzhiyun /*support enhanced frame cap */
74*4882a593Smuzhiyun unsigned char dpcd_efc;
75*4882a593Smuzhiyun struct exynos_dp *regs;
76*4882a593Smuzhiyun };
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun enum analog_power_block {
79*4882a593Smuzhiyun AUX_BLOCK,
80*4882a593Smuzhiyun CH0_BLOCK,
81*4882a593Smuzhiyun CH1_BLOCK,
82*4882a593Smuzhiyun CH2_BLOCK,
83*4882a593Smuzhiyun CH3_BLOCK,
84*4882a593Smuzhiyun ANALOG_TOTAL,
85*4882a593Smuzhiyun POWER_ALL
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun enum pll_status {
89*4882a593Smuzhiyun PLL_UNLOCKED = 0,
90*4882a593Smuzhiyun PLL_LOCKED
91*4882a593Smuzhiyun };
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun enum {
94*4882a593Smuzhiyun COLOR_RGB,
95*4882a593Smuzhiyun COLOR_YCBCR422,
96*4882a593Smuzhiyun COLOR_YCBCR444
97*4882a593Smuzhiyun };
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun enum {
100*4882a593Smuzhiyun VESA,
101*4882a593Smuzhiyun CEA
102*4882a593Smuzhiyun };
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun enum {
105*4882a593Smuzhiyun COLOR_YCBCR601,
106*4882a593Smuzhiyun COLOR_YCBCR709
107*4882a593Smuzhiyun };
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun enum {
110*4882a593Smuzhiyun COLOR_6,
111*4882a593Smuzhiyun COLOR_8,
112*4882a593Smuzhiyun COLOR_10,
113*4882a593Smuzhiyun COLOR_12
114*4882a593Smuzhiyun };
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun enum {
117*4882a593Smuzhiyun DP_LANE_BW_1_62 = 0x06,
118*4882a593Smuzhiyun DP_LANE_BW_2_70 = 0x0a,
119*4882a593Smuzhiyun };
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun enum {
122*4882a593Smuzhiyun DP_LANE_CNT_1 = 1,
123*4882a593Smuzhiyun DP_LANE_CNT_2 = 2,
124*4882a593Smuzhiyun DP_LANE_CNT_4 = 4,
125*4882a593Smuzhiyun };
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun enum {
128*4882a593Smuzhiyun DP_DPCD_REV_10 = 0x10,
129*4882a593Smuzhiyun DP_DPCD_REV_11 = 0x11,
130*4882a593Smuzhiyun };
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun enum {
133*4882a593Smuzhiyun DP_LT_NONE,
134*4882a593Smuzhiyun DP_LT_START,
135*4882a593Smuzhiyun DP_LT_CR,
136*4882a593Smuzhiyun DP_LT_ET,
137*4882a593Smuzhiyun DP_LT_FINISHED,
138*4882a593Smuzhiyun DP_LT_FAIL,
139*4882a593Smuzhiyun };
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun enum {
142*4882a593Smuzhiyun PRE_EMPHASIS_LEVEL_0,
143*4882a593Smuzhiyun PRE_EMPHASIS_LEVEL_1,
144*4882a593Smuzhiyun PRE_EMPHASIS_LEVEL_2,
145*4882a593Smuzhiyun PRE_EMPHASIS_LEVEL_3,
146*4882a593Smuzhiyun };
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun enum {
149*4882a593Smuzhiyun PRBS7,
150*4882a593Smuzhiyun D10_2,
151*4882a593Smuzhiyun TRAINING_PTN1,
152*4882a593Smuzhiyun TRAINING_PTN2,
153*4882a593Smuzhiyun DP_NONE
154*4882a593Smuzhiyun };
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun enum {
157*4882a593Smuzhiyun VOLTAGE_LEVEL_0,
158*4882a593Smuzhiyun VOLTAGE_LEVEL_1,
159*4882a593Smuzhiyun VOLTAGE_LEVEL_2,
160*4882a593Smuzhiyun VOLTAGE_LEVEL_3,
161*4882a593Smuzhiyun };
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun enum pattern_type {
164*4882a593Smuzhiyun NO_PATTERN,
165*4882a593Smuzhiyun COLOR_RAMP,
166*4882a593Smuzhiyun BALCK_WHITE_V_LINES,
167*4882a593Smuzhiyun COLOR_SQUARE,
168*4882a593Smuzhiyun INVALID_PATTERN,
169*4882a593Smuzhiyun COLORBAR_32,
170*4882a593Smuzhiyun COLORBAR_64,
171*4882a593Smuzhiyun WHITE_GRAY_BALCKBAR_32,
172*4882a593Smuzhiyun WHITE_GRAY_BALCKBAR_64,
173*4882a593Smuzhiyun MOBILE_WHITEBAR_32,
174*4882a593Smuzhiyun MOBILE_WHITEBAR_64
175*4882a593Smuzhiyun };
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun enum {
178*4882a593Smuzhiyun CALCULATED_M,
179*4882a593Smuzhiyun REGISTER_M
180*4882a593Smuzhiyun };
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun enum {
183*4882a593Smuzhiyun VIDEO_TIMING_FROM_CAPTURE,
184*4882a593Smuzhiyun VIDEO_TIMING_FROM_REGISTER
185*4882a593Smuzhiyun };
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun struct exynos_dp_platform_data {
189*4882a593Smuzhiyun struct exynos_dp_priv *edp_dev_info;
190*4882a593Smuzhiyun };
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun #ifdef CONFIG_EXYNOS_DP
193*4882a593Smuzhiyun unsigned int exynos_init_dp(void);
194*4882a593Smuzhiyun #else
exynos_init_dp(void)195*4882a593Smuzhiyun unsigned int exynos_init_dp(void)
196*4882a593Smuzhiyun {
197*4882a593Smuzhiyun return 0;
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun #endif
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun #endif /* _DP_INFO_H */
202