1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Common APIs for EXYNOS based board
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2013 Samsung Electronics
5*4882a593Smuzhiyun * Rajeshwari Shinde <rajeshwari.s@samsung.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * See file CREDITS for list of people who contributed to this
8*4882a593Smuzhiyun * project.
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or
11*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License as
12*4882a593Smuzhiyun * published by the Free Software Foundation; either version 2 of
13*4882a593Smuzhiyun * the License, or (at your option) any later version.
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful,
16*4882a593Smuzhiyun * but WITHOUT ANY WARRANTY; without even the implied warranty of
17*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18*4882a593Smuzhiyun * GNU General Public License for more details.
19*4882a593Smuzhiyun *
20*4882a593Smuzhiyun * You should have received a copy of the GNU General Public License
21*4882a593Smuzhiyun * along with this program; if not, write to the Free Software
22*4882a593Smuzhiyun * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23*4882a593Smuzhiyun * MA 02111-1307 USA
24*4882a593Smuzhiyun */
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #include <asm/arch/system.h>
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define DMC_OFFSET 0x10000
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /*
31*4882a593Smuzhiyun * Memory initialization
32*4882a593Smuzhiyun *
33*4882a593Smuzhiyun * @param reset Reset PHY during initialization.
34*4882a593Smuzhiyun */
35*4882a593Smuzhiyun void mem_ctrl_init(int reset);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* System Clock initialization */
38*4882a593Smuzhiyun void system_clock_init(void);
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun /*
41*4882a593Smuzhiyun * Init subsystems according to the reset status
42*4882a593Smuzhiyun *
43*4882a593Smuzhiyun * @return 0 for a normal boot, non-zero for a resume
44*4882a593Smuzhiyun */
45*4882a593Smuzhiyun int do_lowlevel_init(void);
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun void sdelay(unsigned long);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun enum l2_cache_params {
50*4882a593Smuzhiyun CACHE_DATA_RAM_LATENCY_2_CYCLES = (2 << 0),
51*4882a593Smuzhiyun CACHE_DATA_RAM_LATENCY_3_CYCLES = (3 << 0),
52*4882a593Smuzhiyun CACHE_DISABLE_CLEAN_EVICT = (1 << 3),
53*4882a593Smuzhiyun CACHE_DATA_RAM_SETUP = (1 << 5),
54*4882a593Smuzhiyun CACHE_TAG_RAM_LATENCY_2_CYCLES = (2 << 6),
55*4882a593Smuzhiyun CACHE_TAG_RAM_LATENCY_3_CYCLES = (3 << 6),
56*4882a593Smuzhiyun CACHE_ENABLE_HAZARD_DETECT = (1 << 7),
57*4882a593Smuzhiyun CACHE_TAG_RAM_SETUP = (1 << 9),
58*4882a593Smuzhiyun CACHE_ECC_AND_PARITY = (1 << 21),
59*4882a593Smuzhiyun CACHE_ENABLE_FORCE_L2_LOGIC = (1 << 27)
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun #if !defined(CONFIG_SYS_L2CACHE_OFF) && defined(CONFIG_EXYNOS5420)
64*4882a593Smuzhiyun /*
65*4882a593Smuzhiyun * Configure L2CTLR to get timings that keep us from hanging/crashing.
66*4882a593Smuzhiyun *
67*4882a593Smuzhiyun * Must be inline here since low_power_start() is called without a
68*4882a593Smuzhiyun * stack (!).
69*4882a593Smuzhiyun */
configure_l2_ctlr(void)70*4882a593Smuzhiyun static inline void configure_l2_ctlr(void)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun uint32_t val;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun mrc_l2_ctlr(val);
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun val |= CACHE_TAG_RAM_SETUP |
77*4882a593Smuzhiyun CACHE_DATA_RAM_SETUP |
78*4882a593Smuzhiyun CACHE_TAG_RAM_LATENCY_2_CYCLES |
79*4882a593Smuzhiyun CACHE_DATA_RAM_LATENCY_2_CYCLES;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun if (proid_is_exynos5420() || proid_is_exynos5422()) {
82*4882a593Smuzhiyun val |= CACHE_ECC_AND_PARITY |
83*4882a593Smuzhiyun CACHE_TAG_RAM_LATENCY_3_CYCLES |
84*4882a593Smuzhiyun CACHE_DATA_RAM_LATENCY_3_CYCLES;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun mcr_l2_ctlr(val);
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun /*
91*4882a593Smuzhiyun * Configure L2ACTLR.
92*4882a593Smuzhiyun *
93*4882a593Smuzhiyun * Must be inline here since low_power_start() is called without a
94*4882a593Smuzhiyun * stack (!).
95*4882a593Smuzhiyun */
configure_l2_actlr(void)96*4882a593Smuzhiyun static inline void configure_l2_actlr(void)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun uint32_t val;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun if (proid_is_exynos5420() || proid_is_exynos5422()) {
101*4882a593Smuzhiyun mrc_l2_aux_ctlr(val);
102*4882a593Smuzhiyun val |= CACHE_ENABLE_FORCE_L2_LOGIC |
103*4882a593Smuzhiyun CACHE_DISABLE_CLEAN_EVICT;
104*4882a593Smuzhiyun mcr_l2_aux_ctlr(val);
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun #endif
108