1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Processor reset using WDT.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2012 Dmitry Bondar <bond@inmys.ru>
5*4882a593Smuzhiyun * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <asm/io.h>
12*4882a593Smuzhiyun #include <asm/arch/timer_defs.h>
13*4882a593Smuzhiyun #include <asm/arch/hardware.h>
14*4882a593Smuzhiyun
reset_cpu(unsigned long a)15*4882a593Smuzhiyun void reset_cpu(unsigned long a)
16*4882a593Smuzhiyun {
17*4882a593Smuzhiyun struct davinci_timer *const wdttimer =
18*4882a593Smuzhiyun (struct davinci_timer *)DAVINCI_WDOG_BASE;
19*4882a593Smuzhiyun writel(0x08, &wdttimer->tgcr);
20*4882a593Smuzhiyun writel(readl(&wdttimer->tgcr) | 0x03, &wdttimer->tgcr);
21*4882a593Smuzhiyun writel(0, &wdttimer->tim12);
22*4882a593Smuzhiyun writel(0, &wdttimer->tim34);
23*4882a593Smuzhiyun writel(0, &wdttimer->prd12);
24*4882a593Smuzhiyun writel(0, &wdttimer->prd34);
25*4882a593Smuzhiyun writel(readl(&wdttimer->tcr) | 0x40, &wdttimer->tcr);
26*4882a593Smuzhiyun writel(readl(&wdttimer->wdtcr) | 0x4000, &wdttimer->wdtcr);
27*4882a593Smuzhiyun writel(0xa5c64000, &wdttimer->wdtcr);
28*4882a593Smuzhiyun writel(0xda7e4000, &wdttimer->wdtcr);
29*4882a593Smuzhiyun writel(0x4000, &wdttimer->wdtcr);
30*4882a593Smuzhiyun while (1)
31*4882a593Smuzhiyun /*nothing*/;
32*4882a593Smuzhiyun }
33