1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Power and Sleep Controller (PSC) functions.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
5*4882a593Smuzhiyun * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
6*4882a593Smuzhiyun * Copyright (C) 2004 Texas Instruments.
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <common.h>
12*4882a593Smuzhiyun #include <asm/arch/hardware.h>
13*4882a593Smuzhiyun #include <asm/io.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun /*
16*4882a593Smuzhiyun * The PSC manages three inputs to a "module" which may be a peripheral or
17*4882a593Smuzhiyun * CPU. Those inputs are the module's: clock; reset signal; and sometimes
18*4882a593Smuzhiyun * its power domain. For our purposes, we only care whether clock and power
19*4882a593Smuzhiyun * are active, and the module is out of reset.
20*4882a593Smuzhiyun *
21*4882a593Smuzhiyun * DaVinci chips may include two separate power domains: "Always On" and "DSP".
22*4882a593Smuzhiyun * Chips without a DSP generally have only one domain.
23*4882a593Smuzhiyun *
24*4882a593Smuzhiyun * The "Always On" power domain is always on when the chip is on, and is
25*4882a593Smuzhiyun * powered by the VDD pins (on DM644X). The majority of DaVinci modules
26*4882a593Smuzhiyun * lie within the "Always On" power domain.
27*4882a593Smuzhiyun *
28*4882a593Smuzhiyun * A separate domain called the "DSP" domain houses the C64x+ and other video
29*4882a593Smuzhiyun * hardware such as VICP. In some chips, the "DSP" domain is not always on.
30*4882a593Smuzhiyun * The "DSP" power domain is powered by the CVDDDSP pins (on DM644X).
31*4882a593Smuzhiyun */
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /* Works on Always On power domain only (no PD argument) */
lpsc_transition(unsigned int id,unsigned int state)34*4882a593Smuzhiyun static void lpsc_transition(unsigned int id, unsigned int state)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun dv_reg_p mdstat, mdctl, ptstat, ptcmd;
37*4882a593Smuzhiyun #ifdef CONFIG_SOC_DA8XX
38*4882a593Smuzhiyun struct davinci_psc_regs *psc_regs;
39*4882a593Smuzhiyun #endif
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun #ifndef CONFIG_SOC_DA8XX
42*4882a593Smuzhiyun if (id >= DAVINCI_LPSC_GEM)
43*4882a593Smuzhiyun return; /* Don't work on DSP Power Domain */
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
46*4882a593Smuzhiyun mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
47*4882a593Smuzhiyun ptstat = REG_P(PSC_PTSTAT);
48*4882a593Smuzhiyun ptcmd = REG_P(PSC_PTCMD);
49*4882a593Smuzhiyun #else
50*4882a593Smuzhiyun if (id < DAVINCI_LPSC_PSC1_BASE) {
51*4882a593Smuzhiyun if (id >= PSC_PSC0_MODULE_ID_CNT)
52*4882a593Smuzhiyun return;
53*4882a593Smuzhiyun psc_regs = davinci_psc0_regs;
54*4882a593Smuzhiyun mdstat = &psc_regs->psc0.mdstat[id];
55*4882a593Smuzhiyun mdctl = &psc_regs->psc0.mdctl[id];
56*4882a593Smuzhiyun } else {
57*4882a593Smuzhiyun id -= DAVINCI_LPSC_PSC1_BASE;
58*4882a593Smuzhiyun if (id >= PSC_PSC1_MODULE_ID_CNT)
59*4882a593Smuzhiyun return;
60*4882a593Smuzhiyun psc_regs = davinci_psc1_regs;
61*4882a593Smuzhiyun mdstat = &psc_regs->psc1.mdstat[id];
62*4882a593Smuzhiyun mdctl = &psc_regs->psc1.mdctl[id];
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun ptstat = &psc_regs->ptstat;
65*4882a593Smuzhiyun ptcmd = &psc_regs->ptcmd;
66*4882a593Smuzhiyun #endif
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun while (readl(ptstat) & 0x01)
69*4882a593Smuzhiyun continue;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun if ((readl(mdstat) & PSC_MDSTAT_STATE) == state)
72*4882a593Smuzhiyun return; /* Already in that state */
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun writel((readl(mdctl) & ~PSC_MDCTL_NEXT) | state, mdctl);
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun switch (id) {
77*4882a593Smuzhiyun #ifdef CONFIG_SOC_DM644X
78*4882a593Smuzhiyun /* Special treatment for some modules as for sprue14 p.7.4.2 */
79*4882a593Smuzhiyun case DAVINCI_LPSC_VPSSSLV:
80*4882a593Smuzhiyun case DAVINCI_LPSC_EMAC:
81*4882a593Smuzhiyun case DAVINCI_LPSC_EMAC_WRAPPER:
82*4882a593Smuzhiyun case DAVINCI_LPSC_MDIO:
83*4882a593Smuzhiyun case DAVINCI_LPSC_USB:
84*4882a593Smuzhiyun case DAVINCI_LPSC_ATA:
85*4882a593Smuzhiyun case DAVINCI_LPSC_VLYNQ:
86*4882a593Smuzhiyun case DAVINCI_LPSC_UHPI:
87*4882a593Smuzhiyun case DAVINCI_LPSC_DDR_EMIF:
88*4882a593Smuzhiyun case DAVINCI_LPSC_AEMIF:
89*4882a593Smuzhiyun case DAVINCI_LPSC_MMC_SD:
90*4882a593Smuzhiyun case DAVINCI_LPSC_MEMSTICK:
91*4882a593Smuzhiyun case DAVINCI_LPSC_McBSP:
92*4882a593Smuzhiyun case DAVINCI_LPSC_GPIO:
93*4882a593Smuzhiyun writel(readl(mdctl) | 0x200, mdctl);
94*4882a593Smuzhiyun break;
95*4882a593Smuzhiyun #endif
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun writel(0x01, ptcmd);
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun while (readl(ptstat) & 0x01)
101*4882a593Smuzhiyun continue;
102*4882a593Smuzhiyun while ((readl(mdstat) & PSC_MDSTAT_STATE) != state)
103*4882a593Smuzhiyun continue;
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
lpsc_on(unsigned int id)106*4882a593Smuzhiyun void lpsc_on(unsigned int id)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun lpsc_transition(id, 0x03);
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun
lpsc_syncreset(unsigned int id)111*4882a593Smuzhiyun void lpsc_syncreset(unsigned int id)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun lpsc_transition(id, 0x01);
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun
lpsc_disable(unsigned int id)116*4882a593Smuzhiyun void lpsc_disable(unsigned int id)
117*4882a593Smuzhiyun {
118*4882a593Smuzhiyun lpsc_transition(id, 0x0);
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun /* Not all DaVinci chips have a DSP power domain. */
122*4882a593Smuzhiyun #ifdef CONFIG_SOC_DM644X
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun /* If DSPLINK is used, we don't want U-Boot to power on the DSP. */
125*4882a593Smuzhiyun #if !defined(CONFIG_SYS_USE_DSPLINK)
dsp_on(void)126*4882a593Smuzhiyun void dsp_on(void)
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun int i;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun if (REG(PSC_PDSTAT1) & 0x1f)
131*4882a593Smuzhiyun return; /* Already on */
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun REG(PSC_GBLCTL) |= 0x01;
134*4882a593Smuzhiyun REG(PSC_PDCTL1) |= 0x01;
135*4882a593Smuzhiyun REG(PSC_PDCTL1) &= ~0x100;
136*4882a593Smuzhiyun REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
137*4882a593Smuzhiyun REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
138*4882a593Smuzhiyun REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
139*4882a593Smuzhiyun REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
140*4882a593Smuzhiyun REG(PSC_PTCMD) = 0x02;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun for (i = 0; i < 100; i++) {
143*4882a593Smuzhiyun if (REG(PSC_EPCPR) & 0x02)
144*4882a593Smuzhiyun break;
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun REG(PSC_CHP_SHRTSW) = 0x01;
148*4882a593Smuzhiyun REG(PSC_PDCTL1) |= 0x100;
149*4882a593Smuzhiyun REG(PSC_EPCCR) = 0x02;
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun for (i = 0; i < 100; i++) {
152*4882a593Smuzhiyun if (!(REG(PSC_PTSTAT) & 0x02))
153*4882a593Smuzhiyun break;
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun REG(PSC_GBLCTL) &= ~0x1f;
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun #endif /* CONFIG_SYS_USE_DSPLINK */
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun #endif /* have a DSP */
161