1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * DaVinci pinmux functions.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2009 Nick Thompson, GE Fanuc Ltd, <nick.thompson@gefanuc.com>
5*4882a593Smuzhiyun * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6*4882a593Smuzhiyun * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
7*4882a593Smuzhiyun * Copyright (C) 2004 Texas Instruments.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <common.h>
13*4882a593Smuzhiyun #include <asm/arch/hardware.h>
14*4882a593Smuzhiyun #include <asm/io.h>
15*4882a593Smuzhiyun #include <asm/arch/davinci_misc.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun /*
18*4882a593Smuzhiyun * Change the setting of a pin multiplexer field.
19*4882a593Smuzhiyun *
20*4882a593Smuzhiyun * Takes an array of pinmux settings similar to:
21*4882a593Smuzhiyun *
22*4882a593Smuzhiyun * struct pinmux_config uart_pins[] = {
23*4882a593Smuzhiyun * { &davinci_syscfg_regs->pinmux[8], 2, 7 },
24*4882a593Smuzhiyun * { &davinci_syscfg_regs->pinmux[9], 2, 0 }
25*4882a593Smuzhiyun * };
26*4882a593Smuzhiyun *
27*4882a593Smuzhiyun * Stepping through the array, each pinmux[n] register has the given value
28*4882a593Smuzhiyun * set in the pin mux field specified.
29*4882a593Smuzhiyun *
30*4882a593Smuzhiyun * The number of pins in the array must be passed (ARRAY_SIZE can provide
31*4882a593Smuzhiyun * this value conveniently).
32*4882a593Smuzhiyun *
33*4882a593Smuzhiyun * Returns 0 if all field numbers and values are in the correct range,
34*4882a593Smuzhiyun * else returns -1.
35*4882a593Smuzhiyun */
davinci_configure_pin_mux(const struct pinmux_config * pins,const int n_pins)36*4882a593Smuzhiyun int davinci_configure_pin_mux(const struct pinmux_config *pins,
37*4882a593Smuzhiyun const int n_pins)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun int i;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /* check for invalid pinmux values */
42*4882a593Smuzhiyun for (i = 0; i < n_pins; i++) {
43*4882a593Smuzhiyun if (pins[i].field >= PIN_MUX_NUM_FIELDS ||
44*4882a593Smuzhiyun (pins[i].value & ~PIN_MUX_FIELD_MASK) != 0)
45*4882a593Smuzhiyun return -1;
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /* configure the pinmuxes */
49*4882a593Smuzhiyun for (i = 0; i < n_pins; i++) {
50*4882a593Smuzhiyun const int offset = pins[i].field * PIN_MUX_FIELD_SIZE;
51*4882a593Smuzhiyun const unsigned int value = pins[i].value << offset;
52*4882a593Smuzhiyun const unsigned int mask = PIN_MUX_FIELD_MASK << offset;
53*4882a593Smuzhiyun const dv_reg *mux = pins[i].mux;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun writel(value | (readl(mux) & (~mask)), mux);
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun return 0;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /*
62*4882a593Smuzhiyun * Configure multiple pinmux resources.
63*4882a593Smuzhiyun *
64*4882a593Smuzhiyun * Takes an pinmux_resource array of pinmux_config and pin counts:
65*4882a593Smuzhiyun *
66*4882a593Smuzhiyun * const struct pinmux_resource pinmuxes[] = {
67*4882a593Smuzhiyun * PINMUX_ITEM(uart_pins),
68*4882a593Smuzhiyun * PINMUX_ITEM(i2c_pins),
69*4882a593Smuzhiyun * };
70*4882a593Smuzhiyun *
71*4882a593Smuzhiyun * The number of items in the array must be passed (ARRAY_SIZE can provide
72*4882a593Smuzhiyun * this value conveniently).
73*4882a593Smuzhiyun *
74*4882a593Smuzhiyun * Each item entry is configured in the defined order. If configuration
75*4882a593Smuzhiyun * of any item fails, -1 is returned and none of the following items are
76*4882a593Smuzhiyun * configured. On success, 0 is returned.
77*4882a593Smuzhiyun */
davinci_configure_pin_mux_items(const struct pinmux_resource * item,const int n_items)78*4882a593Smuzhiyun int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
79*4882a593Smuzhiyun const int n_items)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun int i;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun for (i = 0; i < n_items; i++) {
84*4882a593Smuzhiyun if (davinci_configure_pin_mux(item[i].pins,
85*4882a593Smuzhiyun item[i].n_pins) != 0)
86*4882a593Smuzhiyun return -1;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun return 0;
90*4882a593Smuzhiyun }
91