1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Miscelaneous DaVinci functions.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2009 Nick Thompson, GE Fanuc Ltd, <nick.thompson@gefanuc.com>
5*4882a593Smuzhiyun * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6*4882a593Smuzhiyun * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
7*4882a593Smuzhiyun * Copyright (C) 2004 Texas Instruments.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <common.h>
13*4882a593Smuzhiyun #include <i2c.h>
14*4882a593Smuzhiyun #include <net.h>
15*4882a593Smuzhiyun #include <asm/arch/hardware.h>
16*4882a593Smuzhiyun #include <asm/io.h>
17*4882a593Smuzhiyun #include <asm/arch/davinci_misc.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #ifndef CONFIG_SPL_BUILD
dram_init(void)22*4882a593Smuzhiyun int dram_init(void)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun /* dram_init must store complete ramsize in gd->ram_size */
25*4882a593Smuzhiyun gd->ram_size = get_ram_size(
26*4882a593Smuzhiyun (void *)CONFIG_SYS_SDRAM_BASE,
27*4882a593Smuzhiyun CONFIG_MAX_RAM_BANK_SIZE);
28*4882a593Smuzhiyun return 0;
29*4882a593Smuzhiyun }
30*4882a593Smuzhiyun
dram_init_banksize(void)31*4882a593Smuzhiyun int dram_init_banksize(void)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
34*4882a593Smuzhiyun gd->bd->bi_dram[0].size = gd->ram_size;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun return 0;
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun #endif
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #ifdef CONFIG_DRIVER_TI_EMAC
41*4882a593Smuzhiyun /*
42*4882a593Smuzhiyun * Read ethernet MAC address from EEPROM for DVEVM compatible boards.
43*4882a593Smuzhiyun * Returns 1 if found, 0 otherwise.
44*4882a593Smuzhiyun */
dvevm_read_mac_address(uint8_t * buf)45*4882a593Smuzhiyun int dvevm_read_mac_address(uint8_t *buf)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun #ifdef CONFIG_SYS_I2C_EEPROM_ADDR
48*4882a593Smuzhiyun /* Read MAC address. */
49*4882a593Smuzhiyun if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x7F00,
50*4882a593Smuzhiyun CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &buf[0], 6))
51*4882a593Smuzhiyun goto i2cerr;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /* Check that MAC address is valid. */
54*4882a593Smuzhiyun if (!is_valid_ethaddr(buf))
55*4882a593Smuzhiyun goto err;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun return 1; /* Found */
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun i2cerr:
60*4882a593Smuzhiyun printf("Read from EEPROM @ 0x%02x failed\n",
61*4882a593Smuzhiyun CONFIG_SYS_I2C_EEPROM_ADDR);
62*4882a593Smuzhiyun err:
63*4882a593Smuzhiyun #endif /* CONFIG_SYS_I2C_EEPROM_ADDR */
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun return 0;
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /*
69*4882a593Smuzhiyun * Set the mii mode as MII or RMII
70*4882a593Smuzhiyun */
71*4882a593Smuzhiyun #if defined(CONFIG_SOC_DA8XX)
davinci_emac_mii_mode_sel(int mode_sel)72*4882a593Smuzhiyun void davinci_emac_mii_mode_sel(int mode_sel)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun int val;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun val = readl(&davinci_syscfg_regs->cfgchip3);
77*4882a593Smuzhiyun if (mode_sel == 0)
78*4882a593Smuzhiyun val &= ~(1 << 8);
79*4882a593Smuzhiyun else
80*4882a593Smuzhiyun val |= (1 << 8);
81*4882a593Smuzhiyun writel(val, &davinci_syscfg_regs->cfgchip3);
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun #endif
84*4882a593Smuzhiyun /*
85*4882a593Smuzhiyun * If there is no MAC address in the environment, then it will be initialized
86*4882a593Smuzhiyun * (silently) from the value in the EEPROM.
87*4882a593Smuzhiyun */
davinci_sync_env_enetaddr(uint8_t * rom_enetaddr)88*4882a593Smuzhiyun void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun uint8_t env_enetaddr[6];
91*4882a593Smuzhiyun int ret;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun ret = eth_env_get_enetaddr_by_index("eth", 0, env_enetaddr);
94*4882a593Smuzhiyun if (!ret) {
95*4882a593Smuzhiyun /*
96*4882a593Smuzhiyun * There is no MAC address in the environment, so we
97*4882a593Smuzhiyun * initialize it from the value in the EEPROM.
98*4882a593Smuzhiyun */
99*4882a593Smuzhiyun debug("### Setting environment from EEPROM MAC address = "
100*4882a593Smuzhiyun "\"%pM\"\n",
101*4882a593Smuzhiyun env_enetaddr);
102*4882a593Smuzhiyun ret = !eth_env_set_enetaddr("ethaddr", rom_enetaddr);
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun if (!ret)
105*4882a593Smuzhiyun printf("Failed to set mac address from EEPROM: %d\n", ret);
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun #endif /* CONFIG_DRIVER_TI_EMAC */
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun #if defined(CONFIG_SOC_DA8XX)
irq_init(void)110*4882a593Smuzhiyun void irq_init(void)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun /*
113*4882a593Smuzhiyun * Mask all IRQs by clearing the global enable and setting
114*4882a593Smuzhiyun * the enable clear for all the 90 interrupts.
115*4882a593Smuzhiyun */
116*4882a593Smuzhiyun writel(0, &davinci_aintc_regs->ger);
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun writel(0, &davinci_aintc_regs->hier);
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun writel(0xffffffff, &davinci_aintc_regs->ecr1);
121*4882a593Smuzhiyun writel(0xffffffff, &davinci_aintc_regs->ecr2);
122*4882a593Smuzhiyun writel(0xffffffff, &davinci_aintc_regs->ecr3);
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun /*
126*4882a593Smuzhiyun * Enable PSC for various peripherals.
127*4882a593Smuzhiyun */
da8xx_configure_lpsc_items(const struct lpsc_resource * item,const int n_items)128*4882a593Smuzhiyun int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
129*4882a593Smuzhiyun const int n_items)
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun int i;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun for (i = 0; i < n_items; i++)
134*4882a593Smuzhiyun lpsc_on(item[i].lpsc_no);
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun return 0;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun #endif
139