1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Intel LXT971/LXT972 PHY Driver for TI DaVinci
3*4882a593Smuzhiyun * (TMS320DM644x) based boards.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * --------------------------------------------------------
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <common.h>
13*4882a593Smuzhiyun #include <net.h>
14*4882a593Smuzhiyun #include <miiphy.h>
15*4882a593Smuzhiyun #include <lxt971a.h>
16*4882a593Smuzhiyun #include <asm/arch/emac_defs.h>
17*4882a593Smuzhiyun #include "../../../drivers/net/davinci_emac.h"
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #ifdef CONFIG_DRIVER_TI_EMAC
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #ifdef CONFIG_CMD_NET
22*4882a593Smuzhiyun
lxt972_is_phy_connected(int phy_addr)23*4882a593Smuzhiyun int lxt972_is_phy_connected(int phy_addr)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun u_int16_t id1, id2;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun if (!davinci_eth_phy_read(phy_addr, MII_PHYSID1, &id1))
28*4882a593Smuzhiyun return(0);
29*4882a593Smuzhiyun if (!davinci_eth_phy_read(phy_addr, MII_PHYSID2, &id2))
30*4882a593Smuzhiyun return(0);
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun if ((id1 == (0x0013)) && ((id2 & 0xfff0) == 0x78e0))
33*4882a593Smuzhiyun return(1);
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun return(0);
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun
lxt972_get_link_speed(int phy_addr)38*4882a593Smuzhiyun int lxt972_get_link_speed(int phy_addr)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun u_int16_t stat1, tmp;
41*4882a593Smuzhiyun volatile emac_regs *emac = (emac_regs *)EMAC_BASE_ADDR;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_STAT2, &stat1))
44*4882a593Smuzhiyun return(0);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun if (!(stat1 & PHY_LXT971_STAT2_LINK)) /* link up? */
47*4882a593Smuzhiyun return(0);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp))
50*4882a593Smuzhiyun return(0);
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun tmp |= PHY_LXT971_DIG_CFG_MII_DRIVE;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun davinci_eth_phy_write(phy_addr, PHY_LXT971_DIG_CFG, tmp);
55*4882a593Smuzhiyun /* Read back */
56*4882a593Smuzhiyun if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp))
57*4882a593Smuzhiyun return(0);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /* Speed doesn't matter, there is no setting for it in EMAC... */
60*4882a593Smuzhiyun if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) {
61*4882a593Smuzhiyun /* set DM644x EMAC for Full Duplex */
62*4882a593Smuzhiyun emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE |
63*4882a593Smuzhiyun EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
64*4882a593Smuzhiyun } else {
65*4882a593Smuzhiyun /*set DM644x EMAC for Half Duplex */
66*4882a593Smuzhiyun emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun return(1);
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun
lxt972_init_phy(int phy_addr)73*4882a593Smuzhiyun int lxt972_init_phy(int phy_addr)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun int ret = 1;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun if (!lxt972_get_link_speed(phy_addr)) {
78*4882a593Smuzhiyun /* Try another time */
79*4882a593Smuzhiyun ret = lxt972_get_link_speed(phy_addr);
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /* Disable PHY Interrupts */
83*4882a593Smuzhiyun davinci_eth_phy_write(phy_addr, PHY_LXT971_INT_ENABLE, 0);
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun return(ret);
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun
lxt972_auto_negotiate(int phy_addr)89*4882a593Smuzhiyun int lxt972_auto_negotiate(int phy_addr)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun u_int16_t tmp;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
94*4882a593Smuzhiyun return(0);
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun /* Restart Auto_negotiation */
97*4882a593Smuzhiyun tmp |= BMCR_ANRESTART;
98*4882a593Smuzhiyun davinci_eth_phy_write(phy_addr, MII_BMCR, tmp);
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun /*check AutoNegotiate complete */
101*4882a593Smuzhiyun udelay (10000);
102*4882a593Smuzhiyun if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
103*4882a593Smuzhiyun return(0);
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun if (!(tmp & BMSR_ANEGCOMPLETE))
106*4882a593Smuzhiyun return(0);
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun return (lxt972_get_link_speed(phy_addr));
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun #endif /* CONFIG_CMD_NET */
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun #endif /* CONFIG_DRIVER_ETHER */
114