1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2009 Texas Instruments Incorporated 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef _GPIO_DEFS_H_ 7*4882a593Smuzhiyun #define _GPIO_DEFS_H_ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef CONFIG_SOC_DA8XX 10*4882a593Smuzhiyun #define DAVINCI_GPIO_BINTEN 0x01C67008 11*4882a593Smuzhiyun #define DAVINCI_GPIO_BANK01 0x01C67010 12*4882a593Smuzhiyun #define DAVINCI_GPIO_BANK23 0x01C67038 13*4882a593Smuzhiyun #define DAVINCI_GPIO_BANK45 0x01C67060 14*4882a593Smuzhiyun #define DAVINCI_GPIO_BANK67 0x01C67088 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #else /* CONFIG_SOC_DA8XX */ 17*4882a593Smuzhiyun #define DAVINCI_GPIO_BINTEN 0x01E26008 18*4882a593Smuzhiyun #define DAVINCI_GPIO_BANK01 0x01E26010 19*4882a593Smuzhiyun #define DAVINCI_GPIO_BANK23 0x01E26038 20*4882a593Smuzhiyun #define DAVINCI_GPIO_BANK45 0x01E26060 21*4882a593Smuzhiyun #define DAVINCI_GPIO_BANK67 0x01E26088 22*4882a593Smuzhiyun #define DAVINCI_GPIO_BANK8 0x01E260B0 23*4882a593Smuzhiyun #endif /* CONFIG_SOC_DA8XX */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun struct davinci_gpio { 26*4882a593Smuzhiyun unsigned int dir; 27*4882a593Smuzhiyun unsigned int out_data; 28*4882a593Smuzhiyun unsigned int set_data; 29*4882a593Smuzhiyun unsigned int clr_data; 30*4882a593Smuzhiyun unsigned int in_data; 31*4882a593Smuzhiyun unsigned int set_rising; 32*4882a593Smuzhiyun unsigned int clr_rising; 33*4882a593Smuzhiyun unsigned int set_falling; 34*4882a593Smuzhiyun unsigned int clr_falling; 35*4882a593Smuzhiyun unsigned int intstat; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun struct davinci_gpio_bank { 39*4882a593Smuzhiyun int num_gpio; 40*4882a593Smuzhiyun unsigned int irq_num; 41*4882a593Smuzhiyun unsigned int irq_mask; 42*4882a593Smuzhiyun unsigned long *in_use; 43*4882a593Smuzhiyun unsigned long base; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define davinci_gpio_bank01 ((struct davinci_gpio *)DAVINCI_GPIO_BANK01) 47*4882a593Smuzhiyun #define davinci_gpio_bank23 ((struct davinci_gpio *)DAVINCI_GPIO_BANK23) 48*4882a593Smuzhiyun #define davinci_gpio_bank45 ((struct davinci_gpio *)DAVINCI_GPIO_BANK45) 49*4882a593Smuzhiyun #define davinci_gpio_bank67 ((struct davinci_gpio *)DAVINCI_GPIO_BANK67) 50*4882a593Smuzhiyun #define davinci_gpio_bank8 ((struct davinci_gpio *)DAVINCI_GPIO_BANK8) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define gpio_status() gpio_info() 53*4882a593Smuzhiyun #define GPIO_NAME_SIZE 20 54*4882a593Smuzhiyun #if defined(CONFIG_SOC_DM644X) 55*4882a593Smuzhiyun /* GPIO0 to GPIO53, omit the V3.3 volts one */ 56*4882a593Smuzhiyun #define MAX_NUM_GPIOS 70 57*4882a593Smuzhiyun #elif defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850) 58*4882a593Smuzhiyun #define MAX_NUM_GPIOS 128 59*4882a593Smuzhiyun #else 60*4882a593Smuzhiyun #define MAX_NUM_GPIOS 144 61*4882a593Smuzhiyun #endif 62*4882a593Smuzhiyun #define GPIO_BANK(gp) (davinci_gpio_bank01 + ((gp) >> 5)) 63*4882a593Smuzhiyun #define GPIO_BIT(gp) ((gp) & 0x1F) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun void gpio_info(void); 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #endif 68