1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Based on: 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * ---------------------------------------------------------------------------- 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * dm644x_emac.h 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * Copyright (C) 2005 Texas Instruments. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * ---------------------------------------------------------------------------- 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 17*4882a593Smuzhiyun * 18*4882a593Smuzhiyun * Modifications: 19*4882a593Smuzhiyun * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot. 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #ifndef _DM644X_EMAC_H_ 23*4882a593Smuzhiyun #define _DM644X_EMAC_H_ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #include <asm/arch/hardware.h> 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #ifdef CONFIG_SOC_DM365 28*4882a593Smuzhiyun #define EMAC_BASE_ADDR (0x01d07000) 29*4882a593Smuzhiyun #define EMAC_WRAPPER_BASE_ADDR (0x01d0a000) 30*4882a593Smuzhiyun #define EMAC_WRAPPER_RAM_ADDR (0x01d08000) 31*4882a593Smuzhiyun #define EMAC_MDIO_BASE_ADDR (0x01d0b000) 32*4882a593Smuzhiyun #define DAVINCI_EMAC_VERSION2 33*4882a593Smuzhiyun #elif defined(CONFIG_SOC_DA8XX) 34*4882a593Smuzhiyun #define EMAC_BASE_ADDR DAVINCI_EMAC_CNTRL_REGS_BASE 35*4882a593Smuzhiyun #define EMAC_WRAPPER_BASE_ADDR DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 36*4882a593Smuzhiyun #define EMAC_WRAPPER_RAM_ADDR DAVINCI_EMAC_WRAPPER_RAM_BASE 37*4882a593Smuzhiyun #define EMAC_MDIO_BASE_ADDR DAVINCI_MDIO_CNTRL_REGS_BASE 38*4882a593Smuzhiyun #define DAVINCI_EMAC_VERSION2 39*4882a593Smuzhiyun #else 40*4882a593Smuzhiyun #define EMAC_BASE_ADDR (0x01c80000) 41*4882a593Smuzhiyun #define EMAC_WRAPPER_BASE_ADDR (0x01c81000) 42*4882a593Smuzhiyun #define EMAC_WRAPPER_RAM_ADDR (0x01c82000) 43*4882a593Smuzhiyun #define EMAC_MDIO_BASE_ADDR (0x01c84000) 44*4882a593Smuzhiyun #endif 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #ifdef CONFIG_SOC_DM646X 47*4882a593Smuzhiyun #define DAVINCI_EMAC_VERSION2 48*4882a593Smuzhiyun #define DAVINCI_EMAC_GIG_ENABLE 49*4882a593Smuzhiyun #endif 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #ifdef CONFIG_SOC_DM646X 52*4882a593Smuzhiyun /* MDIO module input frequency */ 53*4882a593Smuzhiyun #define EMAC_MDIO_BUS_FREQ 76500000 54*4882a593Smuzhiyun /* MDIO clock output frequency */ 55*4882a593Smuzhiyun #define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */ 56*4882a593Smuzhiyun #elif defined(CONFIG_SOC_DM365) 57*4882a593Smuzhiyun /* MDIO module input frequency */ 58*4882a593Smuzhiyun #define EMAC_MDIO_BUS_FREQ 121500000 59*4882a593Smuzhiyun /* MDIO clock output frequency */ 60*4882a593Smuzhiyun #define EMAC_MDIO_CLOCK_FREQ 2200000 /* 2.2 MHz */ 61*4882a593Smuzhiyun #elif defined(CONFIG_SOC_DA8XX) 62*4882a593Smuzhiyun /* MDIO module input frequency */ 63*4882a593Smuzhiyun #define EMAC_MDIO_BUS_FREQ clk_get(DAVINCI_MDIO_CLKID) 64*4882a593Smuzhiyun /* MDIO clock output frequency */ 65*4882a593Smuzhiyun #define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */ 66*4882a593Smuzhiyun #else 67*4882a593Smuzhiyun /* MDIO module input frequency */ 68*4882a593Smuzhiyun #define EMAC_MDIO_BUS_FREQ 99000000 /* PLL/6 - 99 MHz */ 69*4882a593Smuzhiyun /* MDIO clock output frequency */ 70*4882a593Smuzhiyun #define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */ 71*4882a593Smuzhiyun #endif 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define PHY_KSZ8873 (0x00221450) 74*4882a593Smuzhiyun int ksz8873_is_phy_connected(int phy_addr); 75*4882a593Smuzhiyun int ksz8873_get_link_speed(int phy_addr); 76*4882a593Smuzhiyun int ksz8873_init_phy(int phy_addr); 77*4882a593Smuzhiyun int ksz8873_auto_negotiate(int phy_addr); 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #define PHY_LXT972 (0x001378e2) 80*4882a593Smuzhiyun int lxt972_is_phy_connected(int phy_addr); 81*4882a593Smuzhiyun int lxt972_get_link_speed(int phy_addr); 82*4882a593Smuzhiyun int lxt972_init_phy(int phy_addr); 83*4882a593Smuzhiyun int lxt972_auto_negotiate(int phy_addr); 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define PHY_DP83848 (0x20005c90) 86*4882a593Smuzhiyun int dp83848_is_phy_connected(int phy_addr); 87*4882a593Smuzhiyun int dp83848_get_link_speed(int phy_addr); 88*4882a593Smuzhiyun int dp83848_init_phy(int phy_addr); 89*4882a593Smuzhiyun int dp83848_auto_negotiate(int phy_addr); 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #define PHY_ET1011C (0x282f013) 92*4882a593Smuzhiyun int et1011c_get_link_speed(int phy_addr); 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #endif /* _DM644X_EMAC_H_ */ 95