1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * National Semiconductor DP83848 PHY Driver for TI DaVinci
3*4882a593Smuzhiyun * (TMS320DM644x) based boards.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * --------------------------------------------------------
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <common.h>
13*4882a593Smuzhiyun #include <net.h>
14*4882a593Smuzhiyun #include <dp83848.h>
15*4882a593Smuzhiyun #include <asm/arch/emac_defs.h>
16*4882a593Smuzhiyun #include "../../../drivers/net/davinci_emac.h"
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #ifdef CONFIG_DRIVER_TI_EMAC
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #ifdef CONFIG_CMD_NET
21*4882a593Smuzhiyun
dp83848_is_phy_connected(int phy_addr)22*4882a593Smuzhiyun int dp83848_is_phy_connected(int phy_addr)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun u_int16_t id1, id2;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun if (!davinci_eth_phy_read(phy_addr, DP83848_PHYID1_REG, &id1))
27*4882a593Smuzhiyun return(0);
28*4882a593Smuzhiyun if (!davinci_eth_phy_read(phy_addr, DP83848_PHYID2_REG, &id2))
29*4882a593Smuzhiyun return(0);
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun if ((id1 == DP83848_PHYID1_OUI) && (id2 == DP83848_PHYID2_OUI))
32*4882a593Smuzhiyun return(1);
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun return(0);
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun
dp83848_get_link_speed(int phy_addr)37*4882a593Smuzhiyun int dp83848_get_link_speed(int phy_addr)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun u_int16_t tmp;
40*4882a593Smuzhiyun volatile emac_regs* emac = (emac_regs *)EMAC_BASE_ADDR;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun if (!davinci_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp))
43*4882a593Smuzhiyun return(0);
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun if (!(tmp & DP83848_LINK_STATUS)) /* link up? */
46*4882a593Smuzhiyun return(0);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun if (!davinci_eth_phy_read(phy_addr, DP83848_PHY_STAT_REG, &tmp))
49*4882a593Smuzhiyun return(0);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /* Speed doesn't matter, there is no setting for it in EMAC... */
52*4882a593Smuzhiyun if (tmp & DP83848_DUPLEX) {
53*4882a593Smuzhiyun /* set DM644x EMAC for Full Duplex */
54*4882a593Smuzhiyun emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE |
55*4882a593Smuzhiyun EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
56*4882a593Smuzhiyun } else {
57*4882a593Smuzhiyun /*set DM644x EMAC for Half Duplex */
58*4882a593Smuzhiyun emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun return(1);
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun
dp83848_init_phy(int phy_addr)65*4882a593Smuzhiyun int dp83848_init_phy(int phy_addr)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun int ret = 1;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun if (!dp83848_get_link_speed(phy_addr)) {
70*4882a593Smuzhiyun /* Try another time */
71*4882a593Smuzhiyun udelay(100000);
72*4882a593Smuzhiyun ret = dp83848_get_link_speed(phy_addr);
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* Disable PHY Interrupts */
76*4882a593Smuzhiyun davinci_eth_phy_write(phy_addr, DP83848_PHY_INTR_CTRL_REG, 0);
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun return(ret);
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun
dp83848_auto_negotiate(int phy_addr)82*4882a593Smuzhiyun int dp83848_auto_negotiate(int phy_addr)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun u_int16_t tmp;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun if (!davinci_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp))
88*4882a593Smuzhiyun return(0);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun /* Restart Auto_negotiation */
91*4882a593Smuzhiyun tmp &= ~DP83848_AUTONEG; /* remove autonegotiation enable */
92*4882a593Smuzhiyun tmp |= DP83848_ISOLATE; /* Electrically isolate PHY */
93*4882a593Smuzhiyun davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun /* Set the Auto_negotiation Advertisement Register
96*4882a593Smuzhiyun * MII advertising for Next page, 100BaseTxFD and HD,
97*4882a593Smuzhiyun * 10BaseTFD and HD, IEEE 802.3
98*4882a593Smuzhiyun */
99*4882a593Smuzhiyun tmp = DP83848_NP | DP83848_TX_FDX | DP83848_TX_HDX |
100*4882a593Smuzhiyun DP83848_10_FDX | DP83848_10_HDX | DP83848_AN_IEEE_802_3;
101*4882a593Smuzhiyun davinci_eth_phy_write(phy_addr, DP83848_ANA_REG, tmp);
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun /* Read Control Register */
105*4882a593Smuzhiyun if (!davinci_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp))
106*4882a593Smuzhiyun return(0);
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun tmp |= DP83848_SPEED_SELECT | DP83848_AUTONEG | DP83848_DUPLEX_MODE;
109*4882a593Smuzhiyun davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun /* Restart Auto_negotiation */
112*4882a593Smuzhiyun tmp |= DP83848_RESTART_AUTONEG;
113*4882a593Smuzhiyun davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun /*check AutoNegotiate complete */
116*4882a593Smuzhiyun udelay(10000);
117*4882a593Smuzhiyun if (!davinci_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp))
118*4882a593Smuzhiyun return(0);
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun if (!(tmp & DP83848_AUTONEG_COMP))
121*4882a593Smuzhiyun return(0);
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun return (dp83848_get_link_speed(phy_addr));
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun #endif /* CONFIG_CMD_NET */
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun #endif /* CONFIG_DRIVER_ETHER */
129