1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * SoC-specific code for tms320dm644x chips 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 5*4882a593Smuzhiyun * Copyright (C) 2008 Lyrtech <www.lyrtech.com> 6*4882a593Smuzhiyun * Copyright (C) 2004 Texas Instruments. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <common.h> 12*4882a593Smuzhiyun #include <asm/arch/hardware.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define PINMUX0_EMACEN (1 << 31) 16*4882a593Smuzhiyun #define PINMUX0_AECS5 (1 << 11) 17*4882a593Smuzhiyun #define PINMUX0_AECS4 (1 << 10) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define PINMUX1_I2C (1 << 7) 20*4882a593Smuzhiyun #define PINMUX1_UART1 (1 << 1) 21*4882a593Smuzhiyun #define PINMUX1_UART0 (1 << 0) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun davinci_enable_uart0(void)24*4882a593Smuzhiyunvoid davinci_enable_uart0(void) 25*4882a593Smuzhiyun { 26*4882a593Smuzhiyun lpsc_on(DAVINCI_LPSC_UART0); 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* Bringup UART0 out of reset */ 29*4882a593Smuzhiyun REG(UART0_PWREMU_MGMT) = 0x00006001; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* Enable UART0 MUX lines */ 32*4882a593Smuzhiyun REG(PINMUX1) |= PINMUX1_UART0; 33*4882a593Smuzhiyun } 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #ifdef CONFIG_DRIVER_TI_EMAC davinci_enable_emac(void)36*4882a593Smuzhiyunvoid davinci_enable_emac(void) 37*4882a593Smuzhiyun { 38*4882a593Smuzhiyun lpsc_on(DAVINCI_LPSC_EMAC); 39*4882a593Smuzhiyun lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); 40*4882a593Smuzhiyun lpsc_on(DAVINCI_LPSC_MDIO); 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* Enable GIO3.3V cells used for EMAC */ 43*4882a593Smuzhiyun REG(VDD3P3V_PWDN) = 0; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* Enable EMAC. */ 46*4882a593Smuzhiyun REG(PINMUX0) |= PINMUX0_EMACEN; 47*4882a593Smuzhiyun } 48*4882a593Smuzhiyun #endif 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #ifdef CONFIG_SYS_I2C_DAVINCI davinci_enable_i2c(void)51*4882a593Smuzhiyunvoid davinci_enable_i2c(void) 52*4882a593Smuzhiyun { 53*4882a593Smuzhiyun lpsc_on(DAVINCI_LPSC_I2C); 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* Enable I2C pin Mux */ 56*4882a593Smuzhiyun REG(PINMUX1) |= PINMUX1_I2C; 57*4882a593Smuzhiyun } 58*4882a593Smuzhiyun #endif 59*4882a593Smuzhiyun davinci_errata_workarounds(void)60*4882a593Smuzhiyunvoid davinci_errata_workarounds(void) 61*4882a593Smuzhiyun { 62*4882a593Smuzhiyun /* 63*4882a593Smuzhiyun * Workaround for TMS320DM6446 errata 1.3.22: 64*4882a593Smuzhiyun * PSC: PTSTAT Register Does Not Clear After Warm/Maximum Reset 65*4882a593Smuzhiyun * Revision(s) Affected: 1.3 and earlier 66*4882a593Smuzhiyun */ 67*4882a593Smuzhiyun REG(PSC_SILVER_BULLET) = 0; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* 70*4882a593Smuzhiyun * Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR) 71*4882a593Smuzhiyun * as suggested in TMS320DM6446 errata 2.1.2: 72*4882a593Smuzhiyun * 73*4882a593Smuzhiyun * On DM6446 Silicon Revision 2.1 and earlier, under certain conditions 74*4882a593Smuzhiyun * low priority modules can occupy the bus and prevent high priority 75*4882a593Smuzhiyun * modules like the VPSS from getting the required DDR2 throughput. 76*4882a593Smuzhiyun * A hex value of 0x20 should provide a good ARM (cache enabled) 77*4882a593Smuzhiyun * performance and still allow good utilization by the VPSS or other 78*4882a593Smuzhiyun * modules. 79*4882a593Smuzhiyun */ 80*4882a593Smuzhiyun REG(VBPR) = 0x20; 81*4882a593Smuzhiyun } 82