1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Pinmux configurations for the DA830 SoCs 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <common.h> 10*4882a593Smuzhiyun #include <asm/arch/davinci_misc.h> 11*4882a593Smuzhiyun #include <asm/arch/hardware.h> 12*4882a593Smuzhiyun #include <asm/arch/pinmux_defs.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* SPI0 pin muxer settings */ 15*4882a593Smuzhiyun const struct pinmux_config spi0_pins_base[] = { 16*4882a593Smuzhiyun { pinmux(7), 1, 3 }, /* SPI0_SOMI */ 17*4882a593Smuzhiyun { pinmux(7), 1, 4 }, /* SPI0_SIMO */ 18*4882a593Smuzhiyun { pinmux(7), 1, 6 } /* SPI0_CLK */ 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun const struct pinmux_config spi0_pins_scs0[] = { 22*4882a593Smuzhiyun { pinmux(7), 1, 7 } /* SPI0_SCS[0] */ 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun const struct pinmux_config spi0_pins_ena[] = { 26*4882a593Smuzhiyun { pinmux(7), 1, 5 } /* SPI0_ENA */ 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* NAND pin muxer settings */ 30*4882a593Smuzhiyun const struct pinmux_config emifa_pins_cs0[] = { 31*4882a593Smuzhiyun { pinmux(18), 1, 2 } /* EMA_CS[0] */ 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun const struct pinmux_config emifa_pins_cs2[] = { 35*4882a593Smuzhiyun { pinmux(18), 1, 3 } /* EMA_CS[2] */ 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun const struct pinmux_config emifa_pins_cs3[] = { 39*4882a593Smuzhiyun { pinmux(18), 1, 4 } /* EMA_CS[3] */ 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #ifdef CONFIG_USE_NAND 43*4882a593Smuzhiyun const struct pinmux_config emifa_pins[] = { 44*4882a593Smuzhiyun { pinmux(13), 1, 6 }, /* EMA_D[0] */ 45*4882a593Smuzhiyun { pinmux(13), 1, 7 }, /* EMA_D[1] */ 46*4882a593Smuzhiyun { pinmux(14), 1, 0 }, /* EMA_D[2] */ 47*4882a593Smuzhiyun { pinmux(14), 1, 1 }, /* EMA_D[3] */ 48*4882a593Smuzhiyun { pinmux(14), 1, 2 }, /* EMA_D[4] */ 49*4882a593Smuzhiyun { pinmux(14), 1, 3 }, /* EMA_D[5] */ 50*4882a593Smuzhiyun { pinmux(14), 1, 4 }, /* EMA_D[6] */ 51*4882a593Smuzhiyun { pinmux(14), 1, 5 }, /* EMA_D[7] */ 52*4882a593Smuzhiyun { pinmux(14), 1, 6 }, /* EMA_D[8] */ 53*4882a593Smuzhiyun { pinmux(14), 1, 7 }, /* EMA_D[9] */ 54*4882a593Smuzhiyun { pinmux(15), 1, 0 }, /* EMA_D[10] */ 55*4882a593Smuzhiyun { pinmux(15), 1, 1 }, /* EMA_D[11] */ 56*4882a593Smuzhiyun { pinmux(15), 1, 2 }, /* EMA_D[12] */ 57*4882a593Smuzhiyun { pinmux(15), 1, 3 }, /* EMA_D[13] */ 58*4882a593Smuzhiyun { pinmux(15), 1, 4 }, /* EMA_D[14] */ 59*4882a593Smuzhiyun { pinmux(15), 1, 5 }, /* EMA_D[15] */ 60*4882a593Smuzhiyun { pinmux(15), 1, 6 }, /* EMA_A[0] */ 61*4882a593Smuzhiyun { pinmux(15), 1, 7 }, /* EMA_A[1] */ 62*4882a593Smuzhiyun { pinmux(16), 1, 0 }, /* EMA_A[2] */ 63*4882a593Smuzhiyun { pinmux(16), 1, 1 }, /* EMA_A[3] */ 64*4882a593Smuzhiyun { pinmux(16), 1, 2 }, /* EMA_A[4] */ 65*4882a593Smuzhiyun { pinmux(16), 1, 3 }, /* EMA_A[5] */ 66*4882a593Smuzhiyun { pinmux(16), 1, 4 }, /* EMA_A[6] */ 67*4882a593Smuzhiyun { pinmux(16), 1, 5 }, /* EMA_A[7] */ 68*4882a593Smuzhiyun { pinmux(16), 1, 6 }, /* EMA_A[8] */ 69*4882a593Smuzhiyun { pinmux(16), 1, 7 }, /* EMA_A[9] */ 70*4882a593Smuzhiyun { pinmux(17), 1, 0 }, /* EMA_A[10] */ 71*4882a593Smuzhiyun { pinmux(17), 1, 1 }, /* EMA_A[11] */ 72*4882a593Smuzhiyun { pinmux(17), 1, 2 }, /* EMA_A[12] */ 73*4882a593Smuzhiyun { pinmux(17), 1, 3 }, /* EMA_BA[1] */ 74*4882a593Smuzhiyun { pinmux(17), 1, 4 }, /* EMA_BA[0] */ 75*4882a593Smuzhiyun { pinmux(17), 1, 5 }, /* EMA_CLK */ 76*4882a593Smuzhiyun { pinmux(17), 1, 6 }, /* EMA_SDCKE */ 77*4882a593Smuzhiyun { pinmux(17), 1, 7 }, /* EMA_CAS */ 78*4882a593Smuzhiyun { pinmux(18), 1, 0 }, /* EMA_CAS */ 79*4882a593Smuzhiyun { pinmux(18), 1, 1 }, /* EMA_WE */ 80*4882a593Smuzhiyun { pinmux(18), 1, 5 }, /* EMA_OE */ 81*4882a593Smuzhiyun { pinmux(18), 1, 6 }, /* EMA_WE_DQM[1] */ 82*4882a593Smuzhiyun { pinmux(18), 1, 7 }, /* EMA_WE_DQM[0] */ 83*4882a593Smuzhiyun { pinmux(10), 1, 0 } /* Tristate */ 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun #endif 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* EMAC PHY interface pins */ 88*4882a593Smuzhiyun const struct pinmux_config emac_pins_rmii[] = { 89*4882a593Smuzhiyun { pinmux(10), 2, 1 }, /* RMII_TXD[0] */ 90*4882a593Smuzhiyun { pinmux(10), 2, 2 }, /* RMII_TXD[1] */ 91*4882a593Smuzhiyun { pinmux(10), 2, 3 }, /* RMII_TXEN */ 92*4882a593Smuzhiyun { pinmux(10), 2, 4 }, /* RMII_CRS_DV */ 93*4882a593Smuzhiyun { pinmux(10), 2, 5 }, /* RMII_RXD[0] */ 94*4882a593Smuzhiyun { pinmux(10), 2, 6 }, /* RMII_RXD[1] */ 95*4882a593Smuzhiyun { pinmux(10), 2, 7 } /* RMII_RXER */ 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun const struct pinmux_config emac_pins_mdio[] = { 99*4882a593Smuzhiyun { pinmux(11), 2, 0 }, /* MDIO_CLK */ 100*4882a593Smuzhiyun { pinmux(11), 2, 1 } /* MDIO_D */ 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun const struct pinmux_config emac_pins_rmii_clk_source[] = { 104*4882a593Smuzhiyun { pinmux(9), 0, 5 } /* ref.clk from external source */ 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun /* UART2 pin muxer settings */ 108*4882a593Smuzhiyun const struct pinmux_config uart2_pins_txrx[] = { 109*4882a593Smuzhiyun { pinmux(8), 2, 7 }, /* UART2_RXD */ 110*4882a593Smuzhiyun { pinmux(9), 2, 0 } /* UART2_TXD */ 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun /* I2C0 pin muxer settings */ 114*4882a593Smuzhiyun const struct pinmux_config i2c0_pins[] = { 115*4882a593Smuzhiyun { pinmux(8), 2, 3 }, /* I2C0_SDA */ 116*4882a593Smuzhiyun { pinmux(8), 2, 4 } /* I2C0_SCL */ 117*4882a593Smuzhiyun }; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun /* USB0_DRVVBUS pin muxer settings */ 120*4882a593Smuzhiyun const struct pinmux_config usb_pins[] = { 121*4882a593Smuzhiyun { pinmux(9), 1, 1 } /* USB0_DRVVBUS */ 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun #ifdef CONFIG_MMC_DAVINCI 125*4882a593Smuzhiyun /* MMC0 pin muxer settings */ 126*4882a593Smuzhiyun const struct pinmux_config mmc0_pins_8bit[] = { 127*4882a593Smuzhiyun { pinmux(15), 2, 7 }, /* MMCSD0_CLK */ 128*4882a593Smuzhiyun { pinmux(16), 2, 0 }, /* MMCSD0_CMD */ 129*4882a593Smuzhiyun { pinmux(13), 2, 6 }, /* MMCSD0_DAT_0 */ 130*4882a593Smuzhiyun { pinmux(13), 2, 7 }, /* MMCSD0_DAT_1 */ 131*4882a593Smuzhiyun { pinmux(14), 2, 0 }, /* MMCSD0_DAT_2 */ 132*4882a593Smuzhiyun { pinmux(14), 2, 1 }, /* MMCSD0_DAT_3 */ 133*4882a593Smuzhiyun { pinmux(14), 2, 2 }, /* MMCSD0_DAT_4 */ 134*4882a593Smuzhiyun { pinmux(14), 2, 3 }, /* MMCSD0_DAT_5 */ 135*4882a593Smuzhiyun { pinmux(14), 2, 4 }, /* MMCSD0_DAT_6 */ 136*4882a593Smuzhiyun { pinmux(14), 2, 5 } /* MMCSD0_DAT_7 */ 137*4882a593Smuzhiyun /* DA830 supports 8-bit mode */ 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun #endif 140