1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2012 Vikram Narayananan 3*4882a593Smuzhiyun * <vikram186@gmail.com> 4*4882a593Smuzhiyun * (C) Copyright 2012,2015 Stephen Warren 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _BCM2835_GPIO_H_ 10*4882a593Smuzhiyun #define _BCM2835_GPIO_H_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define BCM2835_GPIO_COUNT 54 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define BCM2835_GPIO_FSEL_MASK 0x7 15*4882a593Smuzhiyun #define BCM2835_GPIO_INPUT 0x0 16*4882a593Smuzhiyun #define BCM2835_GPIO_OUTPUT 0x1 17*4882a593Smuzhiyun #define BCM2835_GPIO_ALT0 0x4 18*4882a593Smuzhiyun #define BCM2835_GPIO_ALT1 0x5 19*4882a593Smuzhiyun #define BCM2835_GPIO_ALT2 0x6 20*4882a593Smuzhiyun #define BCM2835_GPIO_ALT3 0x7 21*4882a593Smuzhiyun #define BCM2835_GPIO_ALT4 0x3 22*4882a593Smuzhiyun #define BCM2835_GPIO_ALT5 0x2 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define BCM2835_GPIO_COMMON_BANK(gpio) ((gpio < 32) ? 0 : 1) 25*4882a593Smuzhiyun #define BCM2835_GPIO_COMMON_SHIFT(gpio) (gpio & 0x1f) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define BCM2835_GPIO_FSEL_BANK(gpio) (gpio / 10) 28*4882a593Smuzhiyun #define BCM2835_GPIO_FSEL_SHIFT(gpio) ((gpio % 10) * 3) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun struct bcm2835_gpio_regs { 31*4882a593Smuzhiyun u32 gpfsel[6]; 32*4882a593Smuzhiyun u32 reserved1; 33*4882a593Smuzhiyun u32 gpset[2]; 34*4882a593Smuzhiyun u32 reserved2; 35*4882a593Smuzhiyun u32 gpclr[2]; 36*4882a593Smuzhiyun u32 reserved3; 37*4882a593Smuzhiyun u32 gplev[2]; 38*4882a593Smuzhiyun u32 reserved4; 39*4882a593Smuzhiyun u32 gpeds[2]; 40*4882a593Smuzhiyun u32 reserved5; 41*4882a593Smuzhiyun u32 gpren[2]; 42*4882a593Smuzhiyun u32 reserved6; 43*4882a593Smuzhiyun u32 gpfen[2]; 44*4882a593Smuzhiyun u32 reserved7; 45*4882a593Smuzhiyun u32 gphen[2]; 46*4882a593Smuzhiyun u32 reserved8; 47*4882a593Smuzhiyun u32 gplen[2]; 48*4882a593Smuzhiyun u32 reserved9; 49*4882a593Smuzhiyun u32 gparen[2]; 50*4882a593Smuzhiyun u32 reserved10; 51*4882a593Smuzhiyun u32 gppud; 52*4882a593Smuzhiyun u32 gppudclk[2]; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /** 56*4882a593Smuzhiyun * struct bcm2835_gpio_platdata - GPIO platform description 57*4882a593Smuzhiyun * 58*4882a593Smuzhiyun * @base: Base address of GPIO controller 59*4882a593Smuzhiyun */ 60*4882a593Smuzhiyun struct bcm2835_gpio_platdata { 61*4882a593Smuzhiyun unsigned long base; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun int bcm2835_gpio_get_func_id(struct udevice *dev, unsigned gpio); 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #endif /* _BCM2835_GPIO_H_ */ 67