1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2012 Atmel Corporation. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Static Memory Controllers (SMC) - System peripherals registers. 5*4882a593Smuzhiyun * Based on SAMA5D3 datasheet. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef SAMA5D3_SMC_H 11*4882a593Smuzhiyun #define SAMA5D3_SMC_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifdef __ASSEMBLY__ 14*4882a593Smuzhiyun #define AT91_ASM_SMC_SETUP0 (ATMEL_BASE_SMC + 0x600) 15*4882a593Smuzhiyun #define AT91_ASM_SMC_PULSE0 (ATMEL_BASE_SMC + 0x604) 16*4882a593Smuzhiyun #define AT91_ASM_SMC_CYCLE0 (ATMEL_BASE_SMC + 0x608) 17*4882a593Smuzhiyun #define AT91_ASM_SMC_TIMINGS0 (ATMEL_BASE_SMC + 0x60c) 18*4882a593Smuzhiyun #define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x610) 19*4882a593Smuzhiyun #else 20*4882a593Smuzhiyun struct at91_cs { 21*4882a593Smuzhiyun u32 setup; /* 0x600 SMC Setup Register */ 22*4882a593Smuzhiyun u32 pulse; /* 0x604 SMC Pulse Register */ 23*4882a593Smuzhiyun u32 cycle; /* 0x608 SMC Cycle Register */ 24*4882a593Smuzhiyun u32 timings; /* 0x60C SMC Cycle Register */ 25*4882a593Smuzhiyun u32 mode; /* 0x610 SMC Mode Register */ 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun struct at91_smc { 29*4882a593Smuzhiyun u32 reserved[384]; 30*4882a593Smuzhiyun struct at91_cs cs[4]; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define AT91_SMC_SETUP_NWE(x) (x & 0x3f) 35*4882a593Smuzhiyun #define AT91_SMC_SETUP_NCS_WR(x) ((x & 0x3f) << 8) 36*4882a593Smuzhiyun #define AT91_SMC_SETUP_NRD(x) ((x & 0x3f) << 16) 37*4882a593Smuzhiyun #define AT91_SMC_SETUP_NCS_RD(x) ((x & 0x3f) << 24) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define AT91_SMC_PULSE_NWE(x) (x & 0x3f) 40*4882a593Smuzhiyun #define AT91_SMC_PULSE_NCS_WR(x) ((x & 0x3f) << 8) 41*4882a593Smuzhiyun #define AT91_SMC_PULSE_NRD(x) ((x & 0x3f) << 16) 42*4882a593Smuzhiyun #define AT91_SMC_PULSE_NCS_RD(x) ((x & 0x3f) << 24) 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define AT91_SMC_CYCLE_NWE(x) (x & 0x1ff) 45*4882a593Smuzhiyun #define AT91_SMC_CYCLE_NRD(x) ((x & 0x1ff) << 16) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define AT91_SMC_TIMINGS_TCLR(x) (x & 0xf) 48*4882a593Smuzhiyun #define AT91_SMC_TIMINGS_TADL(x) ((x & 0xf) << 4) 49*4882a593Smuzhiyun #define AT91_SMC_TIMINGS_TAR(x) ((x & 0xf) << 8) 50*4882a593Smuzhiyun #define AT91_SMC_TIMINGS_OCMS(x) ((x & 0x1) << 12) 51*4882a593Smuzhiyun #define AT91_SMC_TIMINGS_TRR(x) ((x & 0xf) << 16) 52*4882a593Smuzhiyun #define AT91_SMC_TIMINGS_TWB(x) ((x & 0xf) << 24) 53*4882a593Smuzhiyun #define AT91_SMC_TIMINGS_RBNSEL(x) ((x & 0xf) << 28) 54*4882a593Smuzhiyun #define AT91_SMC_TIMINGS_NFSEL(x) ((x & 0x1) << 31) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define AT91_SMC_MODE_RM_NCS 0x00000000 57*4882a593Smuzhiyun #define AT91_SMC_MODE_RM_NRD 0x00000001 58*4882a593Smuzhiyun #define AT91_SMC_MODE_WM_NCS 0x00000000 59*4882a593Smuzhiyun #define AT91_SMC_MODE_WM_NWE 0x00000002 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define AT91_SMC_MODE_EXNW_DISABLE 0x00000000 62*4882a593Smuzhiyun #define AT91_SMC_MODE_EXNW_FROZEN 0x00000020 63*4882a593Smuzhiyun #define AT91_SMC_MODE_EXNW_READY 0x00000030 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define AT91_SMC_MODE_BAT 0x00000100 66*4882a593Smuzhiyun #define AT91_SMC_MODE_DBW_8 0x00000000 67*4882a593Smuzhiyun #define AT91_SMC_MODE_DBW_16 0x00001000 68*4882a593Smuzhiyun #define AT91_SMC_MODE_DBW_32 0x00002000 69*4882a593Smuzhiyun #define AT91_SMC_MODE_TDF_CYCLE(x) ((x & 0xf) << 16) 70*4882a593Smuzhiyun #define AT91_SMC_MODE_TDF 0x00100000 71*4882a593Smuzhiyun #define AT91_SMC_MODE_PMEN 0x01000000 72*4882a593Smuzhiyun #define AT91_SMC_MODE_PS_4 0x00000000 73*4882a593Smuzhiyun #define AT91_SMC_MODE_PS_8 0x10000000 74*4882a593Smuzhiyun #define AT91_SMC_MODE_PS_16 0x20000000 75*4882a593Smuzhiyun #define AT91_SMC_MODE_PS_32 0x30000000 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #endif 78