1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Special Function Register (SFR) 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2014 Atmel 5*4882a593Smuzhiyun * Bo Shen <voice.shen@atmel.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __SAMA5_SFR_H 11*4882a593Smuzhiyun #define __SAMA5_SFR_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun struct atmel_sfr { 14*4882a593Smuzhiyun u32 reserved1; /* 0x00 */ 15*4882a593Smuzhiyun u32 ddrcfg; /* 0x04: DDR Configuration Register */ 16*4882a593Smuzhiyun u32 reserved2; /* 0x08 */ 17*4882a593Smuzhiyun u32 reserved3; /* 0x0c */ 18*4882a593Smuzhiyun u32 ohciicr; /* 0x10: OHCI Interrupt Configuration Register */ 19*4882a593Smuzhiyun u32 ohciisr; /* 0x14: OHCI Interrupt Status Register */ 20*4882a593Smuzhiyun u32 reserved4[4]; /* 0x18 ~ 0x24 */ 21*4882a593Smuzhiyun u32 secure; /* 0x28: Security Configuration Register */ 22*4882a593Smuzhiyun u32 reserved5[5]; /* 0x2c ~ 0x3c */ 23*4882a593Smuzhiyun u32 ebicfg; /* 0x40: EBI Configuration Register */ 24*4882a593Smuzhiyun u32 reserved6[2]; /* 0x44 ~ 0x48 */ 25*4882a593Smuzhiyun u32 sn0; /* 0x4c */ 26*4882a593Smuzhiyun u32 sn1; /* 0x50 */ 27*4882a593Smuzhiyun u32 aicredir; /* 0x54 */ 28*4882a593Smuzhiyun u32 l2cc_hramc; /* 0x58 */ 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* Bit field in DDRCFG */ 32*4882a593Smuzhiyun #define ATMEL_SFR_DDRCFG_FDQIEN 0x00010000 33*4882a593Smuzhiyun #define ATMEL_SFR_DDRCFG_FDQSIEN 0x00020000 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* Bit field in EBICFG */ 36*4882a593Smuzhiyun #define AT91_SFR_EBICFG_DRIVE0 (0x3 << 0) 37*4882a593Smuzhiyun #define AT91_SFR_EBICFG_DRIVE0_LOW (0x0 << 0) 38*4882a593Smuzhiyun #define AT91_SFR_EBICFG_DRIVE0_MEDIUM (0x2 << 0) 39*4882a593Smuzhiyun #define AT91_SFR_EBICFG_DRIVE0_HIGH (0x3 << 0) 40*4882a593Smuzhiyun #define AT91_SFR_EBICFG_PULL0 (0x3 << 2) 41*4882a593Smuzhiyun #define AT91_SFR_EBICFG_PULL0_UP (0x0 << 2) 42*4882a593Smuzhiyun #define AT91_SFR_EBICFG_PULL0_NONE (0x1 << 2) 43*4882a593Smuzhiyun #define AT91_SFR_EBICFG_PULL0_DOWN (0x3 << 2) 44*4882a593Smuzhiyun #define AT91_SFR_EBICFG_SCH0 (0x1 << 4) 45*4882a593Smuzhiyun #define AT91_SFR_EBICFG_SCH0_OFF (0x0 << 4) 46*4882a593Smuzhiyun #define AT91_SFR_EBICFG_SCH0_ON (0x1 << 4) 47*4882a593Smuzhiyun #define AT91_SFR_EBICFG_DRIVE1 (0x3 << 8) 48*4882a593Smuzhiyun #define AT91_SFR_EBICFG_DRIVE1_LOW (0x0 << 8) 49*4882a593Smuzhiyun #define AT91_SFR_EBICFG_DRIVE1_MEDIUM (0x2 << 8) 50*4882a593Smuzhiyun #define AT91_SFR_EBICFG_DRIVE1_HIGH (0x3 << 8) 51*4882a593Smuzhiyun #define AT91_SFR_EBICFG_PULL1 (0x3 << 10) 52*4882a593Smuzhiyun #define AT91_SFR_EBICFG_PULL1_UP (0x0 << 10) 53*4882a593Smuzhiyun #define AT91_SFR_EBICFG_PULL1_NONE (0x1 << 10) 54*4882a593Smuzhiyun #define AT91_SFR_EBICFG_PULL1_DOWN (0x3 << 10) 55*4882a593Smuzhiyun #define AT91_SFR_EBICFG_SCH1 (0x1 << 12) 56*4882a593Smuzhiyun #define AT91_SFR_EBICFG_SCH1_OFF (0x0 << 12) 57*4882a593Smuzhiyun #define AT91_SFR_EBICFG_SCH1_ON (0x1 << 12) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* Bit field in AICREDIR */ 60*4882a593Smuzhiyun #define ATMEL_SFR_AICREDIR_NSAIC 0x00000001 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #endif 63