1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * [origin: Linux kernel include/asm-arm/arch-at91/gpio.h]
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2005 HP Labs
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #ifndef __ASM_ARCH_AT91_GPIO_H
10*4882a593Smuzhiyun #define __ASM_ARCH_AT91_GPIO_H
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <asm/io.h>
13*4882a593Smuzhiyun #include <linux/errno.h>
14*4882a593Smuzhiyun #include <asm/arch/at91_pio.h>
15*4882a593Smuzhiyun #include <asm/arch/hardware.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #ifdef CONFIG_ATMEL_LEGACY
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define PIN_BASE 0
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define MAX_GPIO_BANKS 5
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0)
26*4882a593Smuzhiyun #define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1)
27*4882a593Smuzhiyun #define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2)
28*4882a593Smuzhiyun #define AT91_PIN_PA3 (PIN_BASE + 0x00 + 3)
29*4882a593Smuzhiyun #define AT91_PIN_PA4 (PIN_BASE + 0x00 + 4)
30*4882a593Smuzhiyun #define AT91_PIN_PA5 (PIN_BASE + 0x00 + 5)
31*4882a593Smuzhiyun #define AT91_PIN_PA6 (PIN_BASE + 0x00 + 6)
32*4882a593Smuzhiyun #define AT91_PIN_PA7 (PIN_BASE + 0x00 + 7)
33*4882a593Smuzhiyun #define AT91_PIN_PA8 (PIN_BASE + 0x00 + 8)
34*4882a593Smuzhiyun #define AT91_PIN_PA9 (PIN_BASE + 0x00 + 9)
35*4882a593Smuzhiyun #define AT91_PIN_PA10 (PIN_BASE + 0x00 + 10)
36*4882a593Smuzhiyun #define AT91_PIN_PA11 (PIN_BASE + 0x00 + 11)
37*4882a593Smuzhiyun #define AT91_PIN_PA12 (PIN_BASE + 0x00 + 12)
38*4882a593Smuzhiyun #define AT91_PIN_PA13 (PIN_BASE + 0x00 + 13)
39*4882a593Smuzhiyun #define AT91_PIN_PA14 (PIN_BASE + 0x00 + 14)
40*4882a593Smuzhiyun #define AT91_PIN_PA15 (PIN_BASE + 0x00 + 15)
41*4882a593Smuzhiyun #define AT91_PIN_PA16 (PIN_BASE + 0x00 + 16)
42*4882a593Smuzhiyun #define AT91_PIN_PA17 (PIN_BASE + 0x00 + 17)
43*4882a593Smuzhiyun #define AT91_PIN_PA18 (PIN_BASE + 0x00 + 18)
44*4882a593Smuzhiyun #define AT91_PIN_PA19 (PIN_BASE + 0x00 + 19)
45*4882a593Smuzhiyun #define AT91_PIN_PA20 (PIN_BASE + 0x00 + 20)
46*4882a593Smuzhiyun #define AT91_PIN_PA21 (PIN_BASE + 0x00 + 21)
47*4882a593Smuzhiyun #define AT91_PIN_PA22 (PIN_BASE + 0x00 + 22)
48*4882a593Smuzhiyun #define AT91_PIN_PA23 (PIN_BASE + 0x00 + 23)
49*4882a593Smuzhiyun #define AT91_PIN_PA24 (PIN_BASE + 0x00 + 24)
50*4882a593Smuzhiyun #define AT91_PIN_PA25 (PIN_BASE + 0x00 + 25)
51*4882a593Smuzhiyun #define AT91_PIN_PA26 (PIN_BASE + 0x00 + 26)
52*4882a593Smuzhiyun #define AT91_PIN_PA27 (PIN_BASE + 0x00 + 27)
53*4882a593Smuzhiyun #define AT91_PIN_PA28 (PIN_BASE + 0x00 + 28)
54*4882a593Smuzhiyun #define AT91_PIN_PA29 (PIN_BASE + 0x00 + 29)
55*4882a593Smuzhiyun #define AT91_PIN_PA30 (PIN_BASE + 0x00 + 30)
56*4882a593Smuzhiyun #define AT91_PIN_PA31 (PIN_BASE + 0x00 + 31)
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun #define AT91_PIN_PB0 (PIN_BASE + 0x20 + 0)
59*4882a593Smuzhiyun #define AT91_PIN_PB1 (PIN_BASE + 0x20 + 1)
60*4882a593Smuzhiyun #define AT91_PIN_PB2 (PIN_BASE + 0x20 + 2)
61*4882a593Smuzhiyun #define AT91_PIN_PB3 (PIN_BASE + 0x20 + 3)
62*4882a593Smuzhiyun #define AT91_PIN_PB4 (PIN_BASE + 0x20 + 4)
63*4882a593Smuzhiyun #define AT91_PIN_PB5 (PIN_BASE + 0x20 + 5)
64*4882a593Smuzhiyun #define AT91_PIN_PB6 (PIN_BASE + 0x20 + 6)
65*4882a593Smuzhiyun #define AT91_PIN_PB7 (PIN_BASE + 0x20 + 7)
66*4882a593Smuzhiyun #define AT91_PIN_PB8 (PIN_BASE + 0x20 + 8)
67*4882a593Smuzhiyun #define AT91_PIN_PB9 (PIN_BASE + 0x20 + 9)
68*4882a593Smuzhiyun #define AT91_PIN_PB10 (PIN_BASE + 0x20 + 10)
69*4882a593Smuzhiyun #define AT91_PIN_PB11 (PIN_BASE + 0x20 + 11)
70*4882a593Smuzhiyun #define AT91_PIN_PB12 (PIN_BASE + 0x20 + 12)
71*4882a593Smuzhiyun #define AT91_PIN_PB13 (PIN_BASE + 0x20 + 13)
72*4882a593Smuzhiyun #define AT91_PIN_PB14 (PIN_BASE + 0x20 + 14)
73*4882a593Smuzhiyun #define AT91_PIN_PB15 (PIN_BASE + 0x20 + 15)
74*4882a593Smuzhiyun #define AT91_PIN_PB16 (PIN_BASE + 0x20 + 16)
75*4882a593Smuzhiyun #define AT91_PIN_PB17 (PIN_BASE + 0x20 + 17)
76*4882a593Smuzhiyun #define AT91_PIN_PB18 (PIN_BASE + 0x20 + 18)
77*4882a593Smuzhiyun #define AT91_PIN_PB19 (PIN_BASE + 0x20 + 19)
78*4882a593Smuzhiyun #define AT91_PIN_PB20 (PIN_BASE + 0x20 + 20)
79*4882a593Smuzhiyun #define AT91_PIN_PB21 (PIN_BASE + 0x20 + 21)
80*4882a593Smuzhiyun #define AT91_PIN_PB22 (PIN_BASE + 0x20 + 22)
81*4882a593Smuzhiyun #define AT91_PIN_PB23 (PIN_BASE + 0x20 + 23)
82*4882a593Smuzhiyun #define AT91_PIN_PB24 (PIN_BASE + 0x20 + 24)
83*4882a593Smuzhiyun #define AT91_PIN_PB25 (PIN_BASE + 0x20 + 25)
84*4882a593Smuzhiyun #define AT91_PIN_PB26 (PIN_BASE + 0x20 + 26)
85*4882a593Smuzhiyun #define AT91_PIN_PB27 (PIN_BASE + 0x20 + 27)
86*4882a593Smuzhiyun #define AT91_PIN_PB28 (PIN_BASE + 0x20 + 28)
87*4882a593Smuzhiyun #define AT91_PIN_PB29 (PIN_BASE + 0x20 + 29)
88*4882a593Smuzhiyun #define AT91_PIN_PB30 (PIN_BASE + 0x20 + 30)
89*4882a593Smuzhiyun #define AT91_PIN_PB31 (PIN_BASE + 0x20 + 31)
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun #define AT91_PIN_PC0 (PIN_BASE + 0x40 + 0)
92*4882a593Smuzhiyun #define AT91_PIN_PC1 (PIN_BASE + 0x40 + 1)
93*4882a593Smuzhiyun #define AT91_PIN_PC2 (PIN_BASE + 0x40 + 2)
94*4882a593Smuzhiyun #define AT91_PIN_PC3 (PIN_BASE + 0x40 + 3)
95*4882a593Smuzhiyun #define AT91_PIN_PC4 (PIN_BASE + 0x40 + 4)
96*4882a593Smuzhiyun #define AT91_PIN_PC5 (PIN_BASE + 0x40 + 5)
97*4882a593Smuzhiyun #define AT91_PIN_PC6 (PIN_BASE + 0x40 + 6)
98*4882a593Smuzhiyun #define AT91_PIN_PC7 (PIN_BASE + 0x40 + 7)
99*4882a593Smuzhiyun #define AT91_PIN_PC8 (PIN_BASE + 0x40 + 8)
100*4882a593Smuzhiyun #define AT91_PIN_PC9 (PIN_BASE + 0x40 + 9)
101*4882a593Smuzhiyun #define AT91_PIN_PC10 (PIN_BASE + 0x40 + 10)
102*4882a593Smuzhiyun #define AT91_PIN_PC11 (PIN_BASE + 0x40 + 11)
103*4882a593Smuzhiyun #define AT91_PIN_PC12 (PIN_BASE + 0x40 + 12)
104*4882a593Smuzhiyun #define AT91_PIN_PC13 (PIN_BASE + 0x40 + 13)
105*4882a593Smuzhiyun #define AT91_PIN_PC14 (PIN_BASE + 0x40 + 14)
106*4882a593Smuzhiyun #define AT91_PIN_PC15 (PIN_BASE + 0x40 + 15)
107*4882a593Smuzhiyun #define AT91_PIN_PC16 (PIN_BASE + 0x40 + 16)
108*4882a593Smuzhiyun #define AT91_PIN_PC17 (PIN_BASE + 0x40 + 17)
109*4882a593Smuzhiyun #define AT91_PIN_PC18 (PIN_BASE + 0x40 + 18)
110*4882a593Smuzhiyun #define AT91_PIN_PC19 (PIN_BASE + 0x40 + 19)
111*4882a593Smuzhiyun #define AT91_PIN_PC20 (PIN_BASE + 0x40 + 20)
112*4882a593Smuzhiyun #define AT91_PIN_PC21 (PIN_BASE + 0x40 + 21)
113*4882a593Smuzhiyun #define AT91_PIN_PC22 (PIN_BASE + 0x40 + 22)
114*4882a593Smuzhiyun #define AT91_PIN_PC23 (PIN_BASE + 0x40 + 23)
115*4882a593Smuzhiyun #define AT91_PIN_PC24 (PIN_BASE + 0x40 + 24)
116*4882a593Smuzhiyun #define AT91_PIN_PC25 (PIN_BASE + 0x40 + 25)
117*4882a593Smuzhiyun #define AT91_PIN_PC26 (PIN_BASE + 0x40 + 26)
118*4882a593Smuzhiyun #define AT91_PIN_PC27 (PIN_BASE + 0x40 + 27)
119*4882a593Smuzhiyun #define AT91_PIN_PC28 (PIN_BASE + 0x40 + 28)
120*4882a593Smuzhiyun #define AT91_PIN_PC29 (PIN_BASE + 0x40 + 29)
121*4882a593Smuzhiyun #define AT91_PIN_PC30 (PIN_BASE + 0x40 + 30)
122*4882a593Smuzhiyun #define AT91_PIN_PC31 (PIN_BASE + 0x40 + 31)
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun #define AT91_PIN_PD0 (PIN_BASE + 0x60 + 0)
125*4882a593Smuzhiyun #define AT91_PIN_PD1 (PIN_BASE + 0x60 + 1)
126*4882a593Smuzhiyun #define AT91_PIN_PD2 (PIN_BASE + 0x60 + 2)
127*4882a593Smuzhiyun #define AT91_PIN_PD3 (PIN_BASE + 0x60 + 3)
128*4882a593Smuzhiyun #define AT91_PIN_PD4 (PIN_BASE + 0x60 + 4)
129*4882a593Smuzhiyun #define AT91_PIN_PD5 (PIN_BASE + 0x60 + 5)
130*4882a593Smuzhiyun #define AT91_PIN_PD6 (PIN_BASE + 0x60 + 6)
131*4882a593Smuzhiyun #define AT91_PIN_PD7 (PIN_BASE + 0x60 + 7)
132*4882a593Smuzhiyun #define AT91_PIN_PD8 (PIN_BASE + 0x60 + 8)
133*4882a593Smuzhiyun #define AT91_PIN_PD9 (PIN_BASE + 0x60 + 9)
134*4882a593Smuzhiyun #define AT91_PIN_PD10 (PIN_BASE + 0x60 + 10)
135*4882a593Smuzhiyun #define AT91_PIN_PD11 (PIN_BASE + 0x60 + 11)
136*4882a593Smuzhiyun #define AT91_PIN_PD12 (PIN_BASE + 0x60 + 12)
137*4882a593Smuzhiyun #define AT91_PIN_PD13 (PIN_BASE + 0x60 + 13)
138*4882a593Smuzhiyun #define AT91_PIN_PD14 (PIN_BASE + 0x60 + 14)
139*4882a593Smuzhiyun #define AT91_PIN_PD15 (PIN_BASE + 0x60 + 15)
140*4882a593Smuzhiyun #define AT91_PIN_PD16 (PIN_BASE + 0x60 + 16)
141*4882a593Smuzhiyun #define AT91_PIN_PD17 (PIN_BASE + 0x60 + 17)
142*4882a593Smuzhiyun #define AT91_PIN_PD18 (PIN_BASE + 0x60 + 18)
143*4882a593Smuzhiyun #define AT91_PIN_PD19 (PIN_BASE + 0x60 + 19)
144*4882a593Smuzhiyun #define AT91_PIN_PD20 (PIN_BASE + 0x60 + 20)
145*4882a593Smuzhiyun #define AT91_PIN_PD21 (PIN_BASE + 0x60 + 21)
146*4882a593Smuzhiyun #define AT91_PIN_PD22 (PIN_BASE + 0x60 + 22)
147*4882a593Smuzhiyun #define AT91_PIN_PD23 (PIN_BASE + 0x60 + 23)
148*4882a593Smuzhiyun #define AT91_PIN_PD24 (PIN_BASE + 0x60 + 24)
149*4882a593Smuzhiyun #define AT91_PIN_PD25 (PIN_BASE + 0x60 + 25)
150*4882a593Smuzhiyun #define AT91_PIN_PD26 (PIN_BASE + 0x60 + 26)
151*4882a593Smuzhiyun #define AT91_PIN_PD27 (PIN_BASE + 0x60 + 27)
152*4882a593Smuzhiyun #define AT91_PIN_PD28 (PIN_BASE + 0x60 + 28)
153*4882a593Smuzhiyun #define AT91_PIN_PD29 (PIN_BASE + 0x60 + 29)
154*4882a593Smuzhiyun #define AT91_PIN_PD30 (PIN_BASE + 0x60 + 30)
155*4882a593Smuzhiyun #define AT91_PIN_PD31 (PIN_BASE + 0x60 + 31)
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun #define AT91_PIN_PE0 (PIN_BASE + 0x80 + 0)
158*4882a593Smuzhiyun #define AT91_PIN_PE1 (PIN_BASE + 0x80 + 1)
159*4882a593Smuzhiyun #define AT91_PIN_PE2 (PIN_BASE + 0x80 + 2)
160*4882a593Smuzhiyun #define AT91_PIN_PE3 (PIN_BASE + 0x80 + 3)
161*4882a593Smuzhiyun #define AT91_PIN_PE4 (PIN_BASE + 0x80 + 4)
162*4882a593Smuzhiyun #define AT91_PIN_PE5 (PIN_BASE + 0x80 + 5)
163*4882a593Smuzhiyun #define AT91_PIN_PE6 (PIN_BASE + 0x80 + 6)
164*4882a593Smuzhiyun #define AT91_PIN_PE7 (PIN_BASE + 0x80 + 7)
165*4882a593Smuzhiyun #define AT91_PIN_PE8 (PIN_BASE + 0x80 + 8)
166*4882a593Smuzhiyun #define AT91_PIN_PE9 (PIN_BASE + 0x80 + 9)
167*4882a593Smuzhiyun #define AT91_PIN_PE10 (PIN_BASE + 0x80 + 10)
168*4882a593Smuzhiyun #define AT91_PIN_PE11 (PIN_BASE + 0x80 + 11)
169*4882a593Smuzhiyun #define AT91_PIN_PE12 (PIN_BASE + 0x80 + 12)
170*4882a593Smuzhiyun #define AT91_PIN_PE13 (PIN_BASE + 0x80 + 13)
171*4882a593Smuzhiyun #define AT91_PIN_PE14 (PIN_BASE + 0x80 + 14)
172*4882a593Smuzhiyun #define AT91_PIN_PE15 (PIN_BASE + 0x80 + 15)
173*4882a593Smuzhiyun #define AT91_PIN_PE16 (PIN_BASE + 0x80 + 16)
174*4882a593Smuzhiyun #define AT91_PIN_PE17 (PIN_BASE + 0x80 + 17)
175*4882a593Smuzhiyun #define AT91_PIN_PE18 (PIN_BASE + 0x80 + 18)
176*4882a593Smuzhiyun #define AT91_PIN_PE19 (PIN_BASE + 0x80 + 19)
177*4882a593Smuzhiyun #define AT91_PIN_PE20 (PIN_BASE + 0x80 + 20)
178*4882a593Smuzhiyun #define AT91_PIN_PE21 (PIN_BASE + 0x80 + 21)
179*4882a593Smuzhiyun #define AT91_PIN_PE22 (PIN_BASE + 0x80 + 22)
180*4882a593Smuzhiyun #define AT91_PIN_PE23 (PIN_BASE + 0x80 + 23)
181*4882a593Smuzhiyun #define AT91_PIN_PE24 (PIN_BASE + 0x80 + 24)
182*4882a593Smuzhiyun #define AT91_PIN_PE25 (PIN_BASE + 0x80 + 25)
183*4882a593Smuzhiyun #define AT91_PIN_PE26 (PIN_BASE + 0x80 + 26)
184*4882a593Smuzhiyun #define AT91_PIN_PE27 (PIN_BASE + 0x80 + 27)
185*4882a593Smuzhiyun #define AT91_PIN_PE28 (PIN_BASE + 0x80 + 28)
186*4882a593Smuzhiyun #define AT91_PIN_PE29 (PIN_BASE + 0x80 + 29)
187*4882a593Smuzhiyun #define AT91_PIN_PE30 (PIN_BASE + 0x80 + 30)
188*4882a593Smuzhiyun #define AT91_PIN_PE31 (PIN_BASE + 0x80 + 31)
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun static unsigned long at91_pios[] = {
191*4882a593Smuzhiyun ATMEL_BASE_PIOA,
192*4882a593Smuzhiyun ATMEL_BASE_PIOB,
193*4882a593Smuzhiyun ATMEL_BASE_PIOC,
194*4882a593Smuzhiyun #ifdef ATMEL_BASE_PIOD
195*4882a593Smuzhiyun ATMEL_BASE_PIOD,
196*4882a593Smuzhiyun #ifdef ATMEL_BASE_PIOE
197*4882a593Smuzhiyun ATMEL_BASE_PIOE
198*4882a593Smuzhiyun #endif
199*4882a593Smuzhiyun #endif
200*4882a593Smuzhiyun };
201*4882a593Smuzhiyun
pin_to_controller(unsigned pin)202*4882a593Smuzhiyun static inline void *pin_to_controller(unsigned pin)
203*4882a593Smuzhiyun {
204*4882a593Smuzhiyun pin -= PIN_BASE;
205*4882a593Smuzhiyun pin /= 32;
206*4882a593Smuzhiyun return (void *)(at91_pios[pin]);
207*4882a593Smuzhiyun }
208*4882a593Smuzhiyun
pin_to_mask(unsigned pin)209*4882a593Smuzhiyun static inline unsigned pin_to_mask(unsigned pin)
210*4882a593Smuzhiyun {
211*4882a593Smuzhiyun pin -= PIN_BASE;
212*4882a593Smuzhiyun return 1 << (pin % 32);
213*4882a593Smuzhiyun }
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun /* The following macros are need for backward compatibility */
216*4882a593Smuzhiyun #define at91_set_GPIO_periph(x, y) \
217*4882a593Smuzhiyun at91_set_pio_periph((x - PIN_BASE) / 32,(x % 32), y)
218*4882a593Smuzhiyun #define at91_set_A_periph(x, y) \
219*4882a593Smuzhiyun at91_set_a_periph((x - PIN_BASE) / 32,(x % 32), y)
220*4882a593Smuzhiyun #define at91_set_B_periph(x, y) \
221*4882a593Smuzhiyun at91_set_b_periph((x - PIN_BASE) / 32,(x % 32), y)
222*4882a593Smuzhiyun #define at91_set_gpio_output(x, y) \
223*4882a593Smuzhiyun at91_set_pio_output((x - PIN_BASE) / 32,(x % 32), y)
224*4882a593Smuzhiyun #define at91_set_gpio_input(x, y) \
225*4882a593Smuzhiyun at91_set_pio_input((x - PIN_BASE) / 32,(x % 32), y)
226*4882a593Smuzhiyun #endif
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun #define at91_set_gpio_value(x, y) \
229*4882a593Smuzhiyun at91_set_pio_value((x / 32), (x % 32), y)
230*4882a593Smuzhiyun #define at91_get_gpio_value(x) \
231*4882a593Smuzhiyun at91_get_pio_value((x / 32), (x % 32))
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun #define GPIO_PIOA_BASE (0)
234*4882a593Smuzhiyun #define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32)
235*4882a593Smuzhiyun #define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32)
236*4882a593Smuzhiyun #define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32)
237*4882a593Smuzhiyun #define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32)
238*4882a593Smuzhiyun #define GPIO_PIN_PA(x) (GPIO_PIOA_BASE + (x))
239*4882a593Smuzhiyun #define GPIO_PIN_PB(x) (GPIO_PIOB_BASE + (x))
240*4882a593Smuzhiyun #define GPIO_PIN_PC(x) (GPIO_PIOC_BASE + (x))
241*4882a593Smuzhiyun #define GPIO_PIN_PD(x) (GPIO_PIOD_BASE + (x))
242*4882a593Smuzhiyun #define GPIO_PIN_PE(x) (GPIO_PIOE_BASE + (x))
243*4882a593Smuzhiyun
at91_gpio_to_port(unsigned gpio)244*4882a593Smuzhiyun static inline unsigned at91_gpio_to_port(unsigned gpio)
245*4882a593Smuzhiyun {
246*4882a593Smuzhiyun return gpio / 32;
247*4882a593Smuzhiyun }
248*4882a593Smuzhiyun
at91_gpio_to_pin(unsigned gpio)249*4882a593Smuzhiyun static inline unsigned at91_gpio_to_pin(unsigned gpio)
250*4882a593Smuzhiyun {
251*4882a593Smuzhiyun return gpio % 32;
252*4882a593Smuzhiyun }
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun /* Platform data for each GPIO port */
255*4882a593Smuzhiyun struct at91_port_platdata {
256*4882a593Smuzhiyun uint32_t base_addr;
257*4882a593Smuzhiyun const char *bank_name;
258*4882a593Smuzhiyun };
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun #endif /* __ASM_ARCH_AT91_GPIO_H */
261