1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Matrix-centric header file for the AT91SAM9X5 family 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2012-2013 Atmel Corporation. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Memory Controllers (MATRIX, EBI) - System peripherals registers. 7*4882a593Smuzhiyun * Based on AT91SAM9X5 & AT91SAM9N12 preliminary datasheet. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef __AT91SAM9X5_MATRIX_H__ 13*4882a593Smuzhiyun #define __AT91SAM9X5_MATRIX_H__ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* AT91SAM9N12 Matrix definition is a subset of AT91SAM9X5. */ 18*4882a593Smuzhiyun struct at91_matrix { 19*4882a593Smuzhiyun u32 mcfg[16]; 20*4882a593Smuzhiyun u32 scfg[16]; 21*4882a593Smuzhiyun u32 pras[16][2]; 22*4882a593Smuzhiyun u32 mrcr; /* 0x100 Master Remap Control */ 23*4882a593Smuzhiyun u32 filler[5]; 24*4882a593Smuzhiyun #ifdef CONFIG_AT91SAM9X5 25*4882a593Smuzhiyun u32 filler1[2]; 26*4882a593Smuzhiyun #endif 27*4882a593Smuzhiyun /* EBI Chip Select Assignment Register 28*4882a593Smuzhiyun * 0x118: AT91SAM9N12 29*4882a593Smuzhiyun * 0x120: AT91SAM9X5 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun u32 ebicsa; 32*4882a593Smuzhiyun u32 filler4[47]; 33*4882a593Smuzhiyun #ifdef CONFIG_AT91SAM9N12 34*4882a593Smuzhiyun u32 filler5[2]; 35*4882a593Smuzhiyun #endif 36*4882a593Smuzhiyun u32 wpmr; 37*4882a593Smuzhiyun u32 wpsr; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define AT91_MATRIX_ULBT_INFINITE (0 << 0) 43*4882a593Smuzhiyun #define AT91_MATRIX_ULBT_SINGLE (1 << 0) 44*4882a593Smuzhiyun #define AT91_MATRIX_ULBT_FOUR (2 << 0) 45*4882a593Smuzhiyun #define AT91_MATRIX_ULBT_EIGHT (3 << 0) 46*4882a593Smuzhiyun #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) 47*4882a593Smuzhiyun #define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0) 48*4882a593Smuzhiyun #define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0) 49*4882a593Smuzhiyun #define AT91_MATRIX_ULBT_128 (7 << 0) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) 52*4882a593Smuzhiyun #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) 53*4882a593Smuzhiyun #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) 54*4882a593Smuzhiyun #define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define AT91_MATRIX_M0PR_SHIFT 0 57*4882a593Smuzhiyun #define AT91_MATRIX_M1PR_SHIFT 4 58*4882a593Smuzhiyun #define AT91_MATRIX_M2PR_SHIFT 8 59*4882a593Smuzhiyun #define AT91_MATRIX_M3PR_SHIFT 12 60*4882a593Smuzhiyun #define AT91_MATRIX_M4PR_SHIFT 16 61*4882a593Smuzhiyun #define AT91_MATRIX_M5PR_SHIFT 20 62*4882a593Smuzhiyun #define AT91_MATRIX_M6PR_SHIFT 24 63*4882a593Smuzhiyun #define AT91_MATRIX_M7PR_SHIFT 28 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define AT91_MATRIX_M8PR_SHIFT 0 /* register B */ 66*4882a593Smuzhiyun #define AT91_MATRIX_M9PR_SHIFT 4 /* register B */ 67*4882a593Smuzhiyun #define AT91_MATRIX_M10PR_SHIFT 8 /* register B */ 68*4882a593Smuzhiyun #define AT91_MATRIX_M11PR_SHIFT 12 /* register B */ 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define AT91_MATRIX_RCB0 (1 << 0) 71*4882a593Smuzhiyun #define AT91_MATRIX_RCB1 (1 << 1) 72*4882a593Smuzhiyun #define AT91_MATRIX_RCB2 (1 << 2) 73*4882a593Smuzhiyun #define AT91_MATRIX_RCB3 (1 << 3) 74*4882a593Smuzhiyun #define AT91_MATRIX_RCB4 (1 << 4) 75*4882a593Smuzhiyun #define AT91_MATRIX_RCB5 (1 << 5) 76*4882a593Smuzhiyun #define AT91_MATRIX_RCB6 (1 << 6) 77*4882a593Smuzhiyun #define AT91_MATRIX_RCB7 (1 << 7) 78*4882a593Smuzhiyun #define AT91_MATRIX_RCB8 (1 << 8) 79*4882a593Smuzhiyun #define AT91_MATRIX_RCB9 (1 << 9) 80*4882a593Smuzhiyun #define AT91_MATRIX_RCB10 (1 << 10) 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) 83*4882a593Smuzhiyun #define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1) 84*4882a593Smuzhiyun #define AT91_MATRIX_EBI_CS3A_SMC (0 << 3) 85*4882a593Smuzhiyun #define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) 86*4882a593Smuzhiyun #define AT91_MATRIX_EBI_DBPU_ON (0 << 8) 87*4882a593Smuzhiyun #define AT91_MATRIX_EBI_DBPU_OFF (1 << 8) 88*4882a593Smuzhiyun #define AT91_MATRIX_EBI_DBPD_ON (0 << 9) 89*4882a593Smuzhiyun #define AT91_MATRIX_EBI_DBPD_OFF (1 << 9) 90*4882a593Smuzhiyun #define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) 91*4882a593Smuzhiyun #define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) 92*4882a593Smuzhiyun #define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17) 93*4882a593Smuzhiyun #define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17) 94*4882a593Smuzhiyun #define AT91_MATRIX_NFD0_ON_D0 (0 << 24) 95*4882a593Smuzhiyun #define AT91_MATRIX_NFD0_ON_D16 (1 << 24) 96*4882a593Smuzhiyun #define AT91_MATRIX_MP_OFF (0 << 25) 97*4882a593Smuzhiyun #define AT91_MATRIX_MP_ON (1 << 25) 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun #endif 100