1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9rl.h] 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2007 Atmel Corporation 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Common definitions. 7*4882a593Smuzhiyun * Based on AT91SAM9RL datasheet revision A. (Preliminary) 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public 10*4882a593Smuzhiyun * License. See the file COPYING in the main directory of this archive for 11*4882a593Smuzhiyun * more details. 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifndef AT91SAM9RL_H 15*4882a593Smuzhiyun #define AT91SAM9RL_H 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* 18*4882a593Smuzhiyun * defines to be used in other places 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun #define CONFIG_AT91FAMILY /* it's a member of AT91 */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* 23*4882a593Smuzhiyun * Peripheral identifiers/interrupts. 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ 26*4882a593Smuzhiyun #define ATMEL_ID_SYS 1 /* System Peripherals */ 27*4882a593Smuzhiyun #define ATMEL_ID_PIOA 2 /* Parallel IO Controller A */ 28*4882a593Smuzhiyun #define ATMEL_ID_PIOB 3 /* Parallel IO Controller B */ 29*4882a593Smuzhiyun #define ATMEL_ID_PIOC 4 /* Parallel IO Controller C */ 30*4882a593Smuzhiyun #define ATMEL_ID_PIOD 5 /* Parallel IO Controller D */ 31*4882a593Smuzhiyun #define ATMEL_ID_USART0 6 /* USART 0 */ 32*4882a593Smuzhiyun #define ATMEL_ID_USART1 7 /* USART 1 */ 33*4882a593Smuzhiyun #define ATMEL_ID_USART2 8 /* USART 2 */ 34*4882a593Smuzhiyun #define ATMEL_ID_USART3 9 /* USART 3 */ 35*4882a593Smuzhiyun #define ATMEL_ID_MCI 10 /* Multimedia Card Interface */ 36*4882a593Smuzhiyun #define ATMEL_ID_TWI0 11 /* TWI 0 */ 37*4882a593Smuzhiyun #define ATMEL_ID_TWI1 12 /* TWI 1 */ 38*4882a593Smuzhiyun #define ATMEL_ID_SPI 13 /* Serial Peripheral Interface */ 39*4882a593Smuzhiyun #define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */ 40*4882a593Smuzhiyun #define ATMEL_ID_SSC1 15 /* Serial Synchronous Controller 1 */ 41*4882a593Smuzhiyun #define ATMEL_ID_TC0 16 /* Timer Counter 0 */ 42*4882a593Smuzhiyun #define ATMEL_ID_TC1 17 /* Timer Counter 1 */ 43*4882a593Smuzhiyun #define ATMEL_ID_TC2 18 /* Timer Counter 2 */ 44*4882a593Smuzhiyun #define ATMEL_ID_PWMC 19 /* Pulse Width Modulation Controller */ 45*4882a593Smuzhiyun #define ATMEL_ID_TSC 20 /* Touch Screen Controller */ 46*4882a593Smuzhiyun #define ATMEL_ID_DMA 21 /* DMA Controller */ 47*4882a593Smuzhiyun #define ATMEL_ID_UDPHS 22 /* USB Device HS */ 48*4882a593Smuzhiyun #define ATMEL_ID_LCDC 23 /* LCD Controller */ 49*4882a593Smuzhiyun #define ATMEL_ID_AC97C 24 /* AC97 Controller */ 50*4882a593Smuzhiyun #define ATMEL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */ 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* 53*4882a593Smuzhiyun * User Peripheral physical base addresses. 54*4882a593Smuzhiyun */ 55*4882a593Smuzhiyun #define ATMEL_BASE_TCB0 0xfffa0000 56*4882a593Smuzhiyun #define ATMEL_BASE_TC0 0xfffa0000 57*4882a593Smuzhiyun #define ATMEL_BASE_TC1 0xfffa0040 58*4882a593Smuzhiyun #define ATMEL_BASE_TC2 0xfffa0080 59*4882a593Smuzhiyun #define ATMEL_BASE_MCI 0xfffa4000 60*4882a593Smuzhiyun #define ATMEL_BASE_TWI0 0xfffa8000 61*4882a593Smuzhiyun #define ATMEL_BASE_TWI1 0xfffac000 62*4882a593Smuzhiyun #define ATMEL_BASE_USART0 0xfffb0000 63*4882a593Smuzhiyun #define ATMEL_BASE_USART1 0xfffb4000 64*4882a593Smuzhiyun #define ATMEL_BASE_USART2 0xfffb8000 65*4882a593Smuzhiyun #define ATMEL_BASE_USART3 0xfffbc000 66*4882a593Smuzhiyun #define ATMEL_BASE_SSC0 0xfffc0000 67*4882a593Smuzhiyun #define ATMEL_BASE_SSC1 0xfffc4000 68*4882a593Smuzhiyun #define ATMEL_BASE_PWMC 0xfffc8000 69*4882a593Smuzhiyun #define ATMEL_BASE_SPI0 0xfffcc000 70*4882a593Smuzhiyun #define ATMEL_BASE_TSC 0xfffd0000 71*4882a593Smuzhiyun #define ATMEL_BASE_UDPHS 0xfffd4000 72*4882a593Smuzhiyun #define ATMEL_BASE_AC97C 0xfffd8000 73*4882a593Smuzhiyun #define ATMEL_BASE_SYS 0xffffc000 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* 76*4882a593Smuzhiyun * System Peripherals 77*4882a593Smuzhiyun */ 78*4882a593Smuzhiyun #define ATMEL_BASE_DMA 0xffffe600 79*4882a593Smuzhiyun #define ATMEL_BASE_ECC 0xffffe800 80*4882a593Smuzhiyun #define ATMEL_BASE_SDRAMC 0xffffea00 81*4882a593Smuzhiyun #define ATMEL_BASE_SMC 0xffffec00 82*4882a593Smuzhiyun #define ATMEL_BASE_MATRIX 0xffffee00 83*4882a593Smuzhiyun #define ATMEL_BASE_CCFG 0xffffef10 84*4882a593Smuzhiyun #define ATMEL_BASE_AIC 0xfffff000 85*4882a593Smuzhiyun #define ATMEL_BASE_DBGU 0xfffff200 86*4882a593Smuzhiyun #define ATMEL_BASE_PIOA 0xfffff400 87*4882a593Smuzhiyun #define ATMEL_BASE_PIOB 0xfffff600 88*4882a593Smuzhiyun #define ATMEL_BASE_PIOC 0xfffff800 89*4882a593Smuzhiyun #define ATMEL_BASE_PIOD 0xfffffa00 90*4882a593Smuzhiyun #define ATMEL_BASE_PMC 0xfffffc00 91*4882a593Smuzhiyun #define ATMEL_BASE_RSTC 0xfffffd00 92*4882a593Smuzhiyun #define ATMEL_BASE_SHDWC 0xfffffd10 93*4882a593Smuzhiyun #define ATMEL_BASE_RTT 0xfffffd20 94*4882a593Smuzhiyun #define ATMEL_BASE_PIT 0xfffffd30 95*4882a593Smuzhiyun #define ATMEL_BASE_WDT 0xfffffd40 96*4882a593Smuzhiyun #define ATMEL_BASE_SCKCR 0xfffffd50 97*4882a593Smuzhiyun #define ATMEL_BASE_GPBR 0xfffffd60 98*4882a593Smuzhiyun #define ATMEL_BASE_RTC 0xfffffe00 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* 101*4882a593Smuzhiyun * Internal Memory. 102*4882a593Smuzhiyun */ 103*4882a593Smuzhiyun #define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */ 104*4882a593Smuzhiyun #define ATMEL_BASE_ROM 0x00400000 /* Internal ROM base address */ 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #define ATMEL_BASE_LCDC 0x00500000 /* LCD Controller */ 107*4882a593Smuzhiyun #define ATMEL_UHP_BASE 0x00600000 /* USB Device HS controller */ 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun /* 110*4882a593Smuzhiyun * External memory 111*4882a593Smuzhiyun */ 112*4882a593Smuzhiyun #define ATMEL_BASE_CS0 0x10000000 113*4882a593Smuzhiyun #define ATMEL_BASE_CS1 0x20000000 /* SDRAM */ 114*4882a593Smuzhiyun #define ATMEL_BASE_CS2 0x30000000 115*4882a593Smuzhiyun #define ATMEL_BASE_CS3 0x40000000 /* NAND */ 116*4882a593Smuzhiyun #define ATMEL_BASE_CS4 0x50000000 /* Compact Flash Slot 0 */ 117*4882a593Smuzhiyun #define ATMEL_BASE_CS5 0x60000000 /* Compact Flash Slot 1 */ 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun /* Timer */ 120*4882a593Smuzhiyun #define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun /* 123*4882a593Smuzhiyun * Other misc defines 124*4882a593Smuzhiyun */ 125*4882a593Smuzhiyun #define ATMEL_PIO_PORTS 4 /* this SoC has 4 PIO */ 126*4882a593Smuzhiyun #define ATMEL_BASE_PIO ATMEL_BASE_PIOA 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun /* 129*4882a593Smuzhiyun * Cpu Name 130*4882a593Smuzhiyun */ 131*4882a593Smuzhiyun #define ATMEL_CPU_NAME "AT91SAM9RL" 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun #endif 134