1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Matrix-centric header file for the AT91SAM9M1x family 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2008 Atmel Corporation. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Memory Controllers (MATRIX, EBI) - System peripherals registers. 7*4882a593Smuzhiyun * Based on AT91SAM9G45 preliminary datasheet. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef AT91SAM9G45_MATRIX_H 13*4882a593Smuzhiyun #define AT91SAM9G45_MATRIX_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun struct at91_matrix { 18*4882a593Smuzhiyun u32 mcfg[16]; 19*4882a593Smuzhiyun u32 scfg[16]; 20*4882a593Smuzhiyun u32 pras[16][2]; 21*4882a593Smuzhiyun u32 mrcr; /* 0x100 Master Remap Control */ 22*4882a593Smuzhiyun u32 filler[3]; 23*4882a593Smuzhiyun u32 tcmr; 24*4882a593Smuzhiyun u32 filler2; 25*4882a593Smuzhiyun u32 ddrmpr; 26*4882a593Smuzhiyun u32 filler3[3]; 27*4882a593Smuzhiyun u32 ebicsa; 28*4882a593Smuzhiyun u32 filler4[47]; 29*4882a593Smuzhiyun u32 wpmr; 30*4882a593Smuzhiyun u32 wpsr; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define AT91_MATRIX_ULBT_INFINITE (0 << 0) 36*4882a593Smuzhiyun #define AT91_MATRIX_ULBT_SINGLE (1 << 0) 37*4882a593Smuzhiyun #define AT91_MATRIX_ULBT_FOUR (2 << 0) 38*4882a593Smuzhiyun #define AT91_MATRIX_ULBT_EIGHT (3 << 0) 39*4882a593Smuzhiyun #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) 40*4882a593Smuzhiyun #define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0) 41*4882a593Smuzhiyun #define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0) 42*4882a593Smuzhiyun #define AT91_MATRIX_ULBT_128 (7 << 0) 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) 45*4882a593Smuzhiyun #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) 46*4882a593Smuzhiyun #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) 47*4882a593Smuzhiyun #define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define AT91_MATRIX_M0PR_SHIFT 0 50*4882a593Smuzhiyun #define AT91_MATRIX_M1PR_SHIFT 4 51*4882a593Smuzhiyun #define AT91_MATRIX_M2PR_SHIFT 8 52*4882a593Smuzhiyun #define AT91_MATRIX_M3PR_SHIFT 12 53*4882a593Smuzhiyun #define AT91_MATRIX_M4PR_SHIFT 16 54*4882a593Smuzhiyun #define AT91_MATRIX_M5PR_SHIFT 20 55*4882a593Smuzhiyun #define AT91_MATRIX_M6PR_SHIFT 24 56*4882a593Smuzhiyun #define AT91_MATRIX_M7PR_SHIFT 28 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define AT91_MATRIX_M8PR_SHIFT 0 /* register B */ 59*4882a593Smuzhiyun #define AT91_MATRIX_M9PR_SHIFT 4 /* register B */ 60*4882a593Smuzhiyun #define AT91_MATRIX_M10PR_SHIFT 8 /* register B */ 61*4882a593Smuzhiyun #define AT91_MATRIX_M11PR_SHIFT 12 /* register B */ 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define AT91_MATRIX_RCB0 (1 << 0) 64*4882a593Smuzhiyun #define AT91_MATRIX_RCB1 (1 << 1) 65*4882a593Smuzhiyun #define AT91_MATRIX_RCB2 (1 << 2) 66*4882a593Smuzhiyun #define AT91_MATRIX_RCB3 (1 << 3) 67*4882a593Smuzhiyun #define AT91_MATRIX_RCB4 (1 << 4) 68*4882a593Smuzhiyun #define AT91_MATRIX_RCB5 (1 << 5) 69*4882a593Smuzhiyun #define AT91_MATRIX_RCB6 (1 << 6) 70*4882a593Smuzhiyun #define AT91_MATRIX_RCB7 (1 << 7) 71*4882a593Smuzhiyun #define AT91_MATRIX_RCB8 (1 << 8) 72*4882a593Smuzhiyun #define AT91_MATRIX_RCB9 (1 << 9) 73*4882a593Smuzhiyun #define AT91_MATRIX_RCB10 (1 << 10) 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) 76*4882a593Smuzhiyun #define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1) 77*4882a593Smuzhiyun #define AT91_MATRIX_EBI_CS3A_SMC (0 << 3) 78*4882a593Smuzhiyun #define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) 79*4882a593Smuzhiyun #define AT91_MATRIX_EBI_CS4A_SMC (0 << 4) 80*4882a593Smuzhiyun #define AT91_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4) 81*4882a593Smuzhiyun #define AT91_MATRIX_EBI_CS5A_SMC (0 << 5) 82*4882a593Smuzhiyun #define AT91_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5) 83*4882a593Smuzhiyun #define AT91_MATRIX_EBI_DBPU_ON (0 << 8) 84*4882a593Smuzhiyun #define AT91_MATRIX_EBI_DBPU_OFF (1 << 8) 85*4882a593Smuzhiyun #define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) 86*4882a593Smuzhiyun #define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) 87*4882a593Smuzhiyun #define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17) 88*4882a593Smuzhiyun #define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17) 89*4882a593Smuzhiyun #define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18) 90*4882a593Smuzhiyun #define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18) 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #endif 93