1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9_smc.h] 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2007 Andrew Victor 5*4882a593Smuzhiyun * Copyright (C) 2007 Atmel Corporation. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Static Memory Controllers (SMC) - System peripherals registers. 8*4882a593Smuzhiyun * Based on AT91SAM9261 datasheet revision D. 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifndef AT91SAM9_SMC_H 14*4882a593Smuzhiyun #define AT91SAM9_SMC_H 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #ifdef __ASSEMBLY__ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #ifndef ATMEL_BASE_SMC 19*4882a593Smuzhiyun #define ATMEL_BASE_SMC ATMEL_BASE_SMC0 20*4882a593Smuzhiyun #endif 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define AT91_ASM_SMC_SETUP0 ATMEL_BASE_SMC 23*4882a593Smuzhiyun #define AT91_ASM_SMC_PULSE0 (ATMEL_BASE_SMC + 0x04) 24*4882a593Smuzhiyun #define AT91_ASM_SMC_CYCLE0 (ATMEL_BASE_SMC + 0x08) 25*4882a593Smuzhiyun #define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x0C) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #else 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun typedef struct at91_cs { 30*4882a593Smuzhiyun u32 setup; /* 0x00 SMC Setup Register */ 31*4882a593Smuzhiyun u32 pulse; /* 0x04 SMC Pulse Register */ 32*4882a593Smuzhiyun u32 cycle; /* 0x08 SMC Cycle Register */ 33*4882a593Smuzhiyun u32 mode; /* 0x0C SMC Mode Register */ 34*4882a593Smuzhiyun } at91_cs_t; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun typedef struct at91_smc { 37*4882a593Smuzhiyun at91_cs_t cs[8]; 38*4882a593Smuzhiyun } at91_smc_t; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define AT91_SMC_SETUP_NWE(x) (x & 0x3f) 43*4882a593Smuzhiyun #define AT91_SMC_SETUP_NCS_WR(x) ((x & 0x3f) << 8) 44*4882a593Smuzhiyun #define AT91_SMC_SETUP_NRD(x) ((x & 0x3f) << 16) 45*4882a593Smuzhiyun #define AT91_SMC_SETUP_NCS_RD(x) ((x & 0x3f) << 24) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define AT91_SMC_PULSE_NWE(x) (x & 0x7f) 48*4882a593Smuzhiyun #define AT91_SMC_PULSE_NCS_WR(x) ((x & 0x7f) << 8) 49*4882a593Smuzhiyun #define AT91_SMC_PULSE_NRD(x) ((x & 0x7f) << 16) 50*4882a593Smuzhiyun #define AT91_SMC_PULSE_NCS_RD(x) ((x & 0x7f) << 24) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define AT91_SMC_CYCLE_NWE(x) (x & 0x1ff) 53*4882a593Smuzhiyun #define AT91_SMC_CYCLE_NRD(x) ((x & 0x1ff) << 16) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define AT91_SMC_MODE_RM_NCS 0x00000000 56*4882a593Smuzhiyun #define AT91_SMC_MODE_RM_NRD 0x00000001 57*4882a593Smuzhiyun #define AT91_SMC_MODE_WM_NCS 0x00000000 58*4882a593Smuzhiyun #define AT91_SMC_MODE_WM_NWE 0x00000002 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define AT91_SMC_MODE_EXNW_DISABLE 0x00000000 61*4882a593Smuzhiyun #define AT91_SMC_MODE_EXNW_FROZEN 0x00000020 62*4882a593Smuzhiyun #define AT91_SMC_MODE_EXNW_READY 0x00000030 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define AT91_SMC_MODE_BAT 0x00000100 65*4882a593Smuzhiyun #define AT91_SMC_MODE_DBW_8 0x00000000 66*4882a593Smuzhiyun #define AT91_SMC_MODE_DBW_16 0x00001000 67*4882a593Smuzhiyun #define AT91_SMC_MODE_DBW_32 0x00002000 68*4882a593Smuzhiyun #define AT91_SMC_MODE_TDF_CYCLE(x) ((x & 0xf) << 16) 69*4882a593Smuzhiyun #define AT91_SMC_MODE_TDF 0x00100000 70*4882a593Smuzhiyun #define AT91_SMC_MODE_PMEN 0x01000000 71*4882a593Smuzhiyun #define AT91_SMC_MODE_PS_4 0x00000000 72*4882a593Smuzhiyun #define AT91_SMC_MODE_PS_8 0x10000000 73*4882a593Smuzhiyun #define AT91_SMC_MODE_PS_16 0x20000000 74*4882a593Smuzhiyun #define AT91_SMC_MODE_PS_32 0x30000000 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #endif 77