1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263.h] 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) 2007 Atmel Corporation. 5*4882a593Smuzhiyun * (C) Copyright 2010 6*4882a593Smuzhiyun * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Definitions for the SoC: 9*4882a593Smuzhiyun * AT91SAM9263 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifndef AT91SAM9263_H 15*4882a593Smuzhiyun #define AT91SAM9263_H 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* 18*4882a593Smuzhiyun * defines to be used in other places 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun #define CONFIG_AT91FAMILY /* it's a member of AT91 */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* 23*4882a593Smuzhiyun * Peripheral identifiers/interrupts. 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ 26*4882a593Smuzhiyun #define ATMEL_ID_SYS 1 /* System Peripherals */ 27*4882a593Smuzhiyun #define ATMEL_ID_PIOA 2 /* Parallel IO Controller A */ 28*4882a593Smuzhiyun #define ATMEL_ID_PIOB 3 /* Parallel IO Controller B */ 29*4882a593Smuzhiyun #define ATMEL_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */ 30*4882a593Smuzhiyun /* Reserved: 5 */ 31*4882a593Smuzhiyun /* Reserved: 6 */ 32*4882a593Smuzhiyun #define ATMEL_ID_USART0 7 /* USART 0 */ 33*4882a593Smuzhiyun #define ATMEL_ID_USART1 8 /* USART 1 */ 34*4882a593Smuzhiyun #define ATMEL_ID_USART2 9 /* USART 2 */ 35*4882a593Smuzhiyun #define ATMEL_ID_MCI0 10 /* Multimedia Card Interface 0 */ 36*4882a593Smuzhiyun #define ATMEL_ID_MCI1 11 /* Multimedia Card Interface 1 */ 37*4882a593Smuzhiyun #define ATMEL_ID_CAN 12 /* CAN */ 38*4882a593Smuzhiyun #define ATMEL_ID_TWI 13 /* Two-Wire Interface */ 39*4882a593Smuzhiyun #define ATMEL_ID_SPI0 14 /* Serial Peripheral Interface 0 */ 40*4882a593Smuzhiyun #define ATMEL_ID_SPI1 15 /* Serial Peripheral Interface 1 */ 41*4882a593Smuzhiyun #define ATMEL_ID_SSC0 16 /* Serial Synchronous Controller 0 */ 42*4882a593Smuzhiyun #define ATMEL_ID_SSC1 17 /* Serial Synchronous Controller 1 */ 43*4882a593Smuzhiyun #define ATMEL_ID_AC97C 18 /* AC97 Controller */ 44*4882a593Smuzhiyun #define ATMEL_ID_TCB 19 /* Timer Counter 0, 1 and 2 */ 45*4882a593Smuzhiyun #define ATMEL_ID_PWMC 20 /* Pulse Width Modulation Controller */ 46*4882a593Smuzhiyun #define ATMEL_ID_EMAC 21 /* Ethernet */ 47*4882a593Smuzhiyun /* Reserved: 22 */ 48*4882a593Smuzhiyun #define ATMEL_ID_2DGE 23 /* 2D Graphic Engine */ 49*4882a593Smuzhiyun #define ATMEL_ID_UDP 24 /* USB Device Port */ 50*4882a593Smuzhiyun #define ATMEL_ID_ISI 25 /* Image Sensor Interface */ 51*4882a593Smuzhiyun #define ATMEL_ID_LCDC 26 /* LCD Controller */ 52*4882a593Smuzhiyun #define ATMEL_ID_DMA 27 /* DMA Controller */ 53*4882a593Smuzhiyun /* Reserved: 28 */ 54*4882a593Smuzhiyun #define ATMEL_ID_UHP 29 /* USB Host port */ 55*4882a593Smuzhiyun #define ATMEL_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ 56*4882a593Smuzhiyun #define ATMEL_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* 59*4882a593Smuzhiyun * User Peripherals physical base addresses. 60*4882a593Smuzhiyun */ 61*4882a593Smuzhiyun #define ATMEL_BASE_UDP 0xfff78000 62*4882a593Smuzhiyun #define ATMEL_BASE_TCB0 0xfff7c000 63*4882a593Smuzhiyun #define ATMEL_BASE_TC0 0xfff7c000 64*4882a593Smuzhiyun #define ATMEL_BASE_TC1 0xfff7c040 65*4882a593Smuzhiyun #define ATMEL_BASE_TC2 0xfff7c080 66*4882a593Smuzhiyun #define ATMEL_BASE_MCI0 0xfff80000 67*4882a593Smuzhiyun #define ATMEL_BASE_MCI1 0xfff84000 68*4882a593Smuzhiyun #define ATMEL_BASE_TWI 0xfff88000 69*4882a593Smuzhiyun #define ATMEL_BASE_USART0 0xfff8c000 70*4882a593Smuzhiyun #define ATMEL_BASE_USART1 0xfff90000 71*4882a593Smuzhiyun #define ATMEL_BASE_USART2 0xfff94000 72*4882a593Smuzhiyun #define ATMEL_BASE_SSC0 0xfff98000 73*4882a593Smuzhiyun #define ATMEL_BASE_SSC1 0xfff9c000 74*4882a593Smuzhiyun #define ATMEL_BASE_AC97C 0xfffa0000 75*4882a593Smuzhiyun #define ATMEL_BASE_SPI0 0xfffa4000 76*4882a593Smuzhiyun #define ATMEL_BASE_SPI1 0xfffa8000 77*4882a593Smuzhiyun #define ATMEL_BASE_CAN 0xfffac000 78*4882a593Smuzhiyun #define ATMEL_BASE_PWMC 0xfffb8000 79*4882a593Smuzhiyun #define ATMEL_BASE_EMAC 0xfffbc000 80*4882a593Smuzhiyun #define ATMEL_BASE_ISI 0xfffc4000 81*4882a593Smuzhiyun #define ATMEL_BASE_2DGE 0xfffc8000 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* 84*4882a593Smuzhiyun * System Peripherals physical base addresses. 85*4882a593Smuzhiyun */ 86*4882a593Smuzhiyun #define ATMEL_BASE_ECC0 0xffffe000 87*4882a593Smuzhiyun #define ATMEL_BASE_SDRAMC0 0xffffe200 88*4882a593Smuzhiyun #define ATMEL_BASE_SMC0 0xffffe400 89*4882a593Smuzhiyun #define ATMEL_BASE_ECC1 0xffffe600 90*4882a593Smuzhiyun #define ATMEL_BASE_SDRAMC1 0xffffe800 91*4882a593Smuzhiyun #define ATMEL_BASE_SMC1 0xffffea00 92*4882a593Smuzhiyun #define ATMEL_BASE_MATRIX 0xffffec00 93*4882a593Smuzhiyun #define ATMEL_BASE_CCFG 0xffffed10 94*4882a593Smuzhiyun #define ATMEL_BASE_DBGU 0xffffee00 95*4882a593Smuzhiyun #define ATMEL_BASE_AIC 0xfffff000 96*4882a593Smuzhiyun #define ATMEL_BASE_PIOA 0xfffff200 97*4882a593Smuzhiyun #define ATMEL_BASE_PIOB 0xfffff400 98*4882a593Smuzhiyun #define ATMEL_BASE_PIOC 0xfffff600 99*4882a593Smuzhiyun #define ATMEL_BASE_PIOD 0xfffff800 100*4882a593Smuzhiyun #define ATMEL_BASE_PIOE 0xfffffa00 101*4882a593Smuzhiyun #define ATMEL_BASE_PMC 0xfffffc00 102*4882a593Smuzhiyun #define ATMEL_BASE_RSTC 0xfffffd00 103*4882a593Smuzhiyun #define ATMEL_BASE_SHDWC 0xfffffd10 104*4882a593Smuzhiyun #define ATMEL_BASE_RTT0 0xfffffd20 105*4882a593Smuzhiyun #define ATMEL_BASE_PIT 0xfffffd30 106*4882a593Smuzhiyun #define ATMEL_BASE_WDT 0xfffffd40 107*4882a593Smuzhiyun #define ATMEL_BASE_RTT1 0xfffffd50 108*4882a593Smuzhiyun #define ATMEL_BASE_GPBR 0xfffffd60 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* 111*4882a593Smuzhiyun * Internal Memory. 112*4882a593Smuzhiyun */ 113*4882a593Smuzhiyun #define ATMEL_BASE_SRAM0 0x00300000 /* Internal SRAM 0 */ 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #define ATMEL_BASE_ROM 0x00400000 /* Internal ROM */ 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #define ATMEL_BASE_SRAM1 0x00500000 /* Internal SRAM 1 */ 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #define ATMEL_BASE_LCDC 0x00700000 /* LCD Controller */ 120*4882a593Smuzhiyun #define ATMEL_BASE_DMAC 0x00800000 /* DMA Controller */ 121*4882a593Smuzhiyun #define ATMEL_BASE_UHP 0x00a00000 /* USB Host controller */ 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun /* 124*4882a593Smuzhiyun * External memory 125*4882a593Smuzhiyun */ 126*4882a593Smuzhiyun #define ATMEL_BASE_CS0 0x10000000 /* typically NOR */ 127*4882a593Smuzhiyun #define ATMEL_BASE_CS1 0x20000000 /* SDRAM */ 128*4882a593Smuzhiyun #define ATMEL_BASE_CS2 0x30000000 129*4882a593Smuzhiyun #define ATMEL_BASE_CS3 0x40000000 /* typically NAND */ 130*4882a593Smuzhiyun #define ATMEL_BASE_CS4 0x50000000 131*4882a593Smuzhiyun #define ATMEL_BASE_CS5 0x60000000 132*4882a593Smuzhiyun #define ATMEL_BASE_CS6 0x70000000 133*4882a593Smuzhiyun #define ATMEL_BASE_CS7 0x80000000 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun /* Timer */ 136*4882a593Smuzhiyun #define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun /* 139*4882a593Smuzhiyun * Other misc defines 140*4882a593Smuzhiyun */ 141*4882a593Smuzhiyun #define ATMEL_PIO_PORTS 5 /* this SoCs has 5 PIO */ 142*4882a593Smuzhiyun #define ATMEL_BASE_PIO ATMEL_BASE_PIOA 143*4882a593Smuzhiyun #define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun /* 146*4882a593Smuzhiyun * Cpu Name 147*4882a593Smuzhiyun */ 148*4882a593Smuzhiyun #define ATMEL_CPU_NAME "AT91SAM9263" 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun #endif 151