1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261.h] 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) SAN People 5*4882a593Smuzhiyun * (C) Copyright 2010 6*4882a593Smuzhiyun * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Definitions for the SoCs: 9*4882a593Smuzhiyun * AT91SAM9261, AT91SAM9G10 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * Note that those SoCs are mostly software and pin compatible, 12*4882a593Smuzhiyun * therefore this file applies to all of them. Differences between 13*4882a593Smuzhiyun * those SoCs are concentrated at the end of this file. 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #ifndef AT91SAM9261_H 19*4882a593Smuzhiyun #define AT91SAM9261_H 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* 22*4882a593Smuzhiyun * defines to be used in other places 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun #define CONFIG_AT91FAMILY /* it's a member of AT91 */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* 27*4882a593Smuzhiyun * Peripheral identifiers/interrupts. 28*4882a593Smuzhiyun */ 29*4882a593Smuzhiyun #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ 30*4882a593Smuzhiyun #define ATMEL_ID_SYS 1 /* System Peripherals */ 31*4882a593Smuzhiyun #define ATMEL_ID_PIOA 2 /* Parallel IO Controller A */ 32*4882a593Smuzhiyun #define ATMEL_ID_PIOB 3 /* Parallel IO Controller B */ 33*4882a593Smuzhiyun #define ATMEL_ID_PIOC 4 /* Parallel IO Controller C */ 34*4882a593Smuzhiyun /* Reserved: 5 */ 35*4882a593Smuzhiyun #define ATMEL_ID_USART0 6 /* USART 0 */ 36*4882a593Smuzhiyun #define ATMEL_ID_USART1 7 /* USART 1 */ 37*4882a593Smuzhiyun #define ATMEL_ID_USART2 8 /* USART 2 */ 38*4882a593Smuzhiyun #define ATMEL_ID_MCI 9 /* Multimedia Card Interface */ 39*4882a593Smuzhiyun #define ATMEL_ID_UDP 10 /* USB Device Port */ 40*4882a593Smuzhiyun #define ATMEL_ID_TWI0 11 /* Two-Wire Interface 0 */ 41*4882a593Smuzhiyun #define ATMEL_ID_SPI0 12 /* Serial Peripheral Interface 0 */ 42*4882a593Smuzhiyun #define ATMEL_ID_SPI1 13 /* Serial Peripheral Interface 1 */ 43*4882a593Smuzhiyun #define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */ 44*4882a593Smuzhiyun #define ATMEL_ID_SSC1 15 /* Serial Synchronous Controller 1 */ 45*4882a593Smuzhiyun #define ATMEL_ID_SSC2 16 /* Serial Synchronous Controller 2 */ 46*4882a593Smuzhiyun #define ATMEL_ID_TC0 17 /* Timer Counter 0 */ 47*4882a593Smuzhiyun #define ATMEL_ID_TC1 18 /* Timer Counter 1 */ 48*4882a593Smuzhiyun #define ATMEL_ID_TC2 19 /* Timer Counter 2 */ 49*4882a593Smuzhiyun #define ATMEL_ID_UHP 20 /* USB Host port */ 50*4882a593Smuzhiyun #define ATMEL_ID_LCDC 21 /* LDC Controller */ 51*4882a593Smuzhiyun /* Reserved: 22-28 */ 52*4882a593Smuzhiyun #define ATMEL_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ 53*4882a593Smuzhiyun #define ATMEL_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ 54*4882a593Smuzhiyun #define ATMEL_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* 57*4882a593Smuzhiyun * User Peripherals physical base addresses. 58*4882a593Smuzhiyun */ 59*4882a593Smuzhiyun #define ATMEL_BASE_TCB0 0xfffa0000 60*4882a593Smuzhiyun #define ATMEL_BASE_TC0 0xfffa0000 61*4882a593Smuzhiyun #define ATMEL_BASE_TC1 0xfffa0040 62*4882a593Smuzhiyun #define ATMEL_BASE_TC2 0xfffa0080 63*4882a593Smuzhiyun #define ATMEL_BASE_UDP0 0xfffa4000 64*4882a593Smuzhiyun #define ATMEL_BASE_MCI 0xfffa8000 65*4882a593Smuzhiyun #define ATMEL_BASE_TWI0 0xfffac000 66*4882a593Smuzhiyun #define ATMEL_BASE_USART0 0xfffb0000 67*4882a593Smuzhiyun #define ATMEL_BASE_USART1 0xfffb4000 68*4882a593Smuzhiyun #define ATMEL_BASE_USART2 0xfffb8000 69*4882a593Smuzhiyun #define ATMEL_BASE_SSC0 0xfffbc000 70*4882a593Smuzhiyun #define ATMEL_BASE_SSC1 0xfffc0000 71*4882a593Smuzhiyun #define ATMEL_BASE_SSC2 0xfffc4000 72*4882a593Smuzhiyun #define ATMEL_BASE_SPI0 0xfffc8000 73*4882a593Smuzhiyun #define ATMEL_BASE_SPI1 0xfffcc000 74*4882a593Smuzhiyun /* Reserved: 0xfffc4000 - 0xffffe9ff */ 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* 77*4882a593Smuzhiyun * System Peripherals physical base addresses. 78*4882a593Smuzhiyun */ 79*4882a593Smuzhiyun #define ATMEL_BASE_SYS 0xffffea00 80*4882a593Smuzhiyun #define ATMEL_BASE_SDRAMC 0xffffea00 81*4882a593Smuzhiyun #define ATMEL_BASE_SMC 0xffffec00 82*4882a593Smuzhiyun #define ATMEL_BASE_MATRIX 0xffffee00 83*4882a593Smuzhiyun #define ATMEL_BASE_AIC 0xfffff000 84*4882a593Smuzhiyun #define ATMEL_BASE_DBGU 0xfffff200 85*4882a593Smuzhiyun #define ATMEL_BASE_PIOA 0xfffff400 86*4882a593Smuzhiyun #define ATMEL_BASE_PIOB 0xfffff600 87*4882a593Smuzhiyun #define ATMEL_BASE_PIOC 0xfffff800 88*4882a593Smuzhiyun #define ATMEL_BASE_PMC 0xfffffc00 89*4882a593Smuzhiyun #define ATMEL_BASE_RSTC 0xfffffd00 90*4882a593Smuzhiyun #define ATMEL_BASE_SHDWN 0xfffffd10 91*4882a593Smuzhiyun #define ATMEL_BASE_RTT 0xfffffd20 92*4882a593Smuzhiyun #define ATMEL_BASE_PIT 0xfffffd30 93*4882a593Smuzhiyun #define ATMEL_BASE_WDT 0xfffffd40 94*4882a593Smuzhiyun #define ATMEL_BASE_GPBR 0xfffffd50 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* 97*4882a593Smuzhiyun * Internal Memory common on all these SoCs 98*4882a593Smuzhiyun */ 99*4882a593Smuzhiyun #define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */ 100*4882a593Smuzhiyun #define ATMEL_SIZE_SRAM 0x00028000 /* Internal SRAM size (160Kb) */ 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #define ATMEL_BASE_ROM 0x00400000 /* Internal ROM base address */ 103*4882a593Smuzhiyun #define ATMEL_SIZE_ROM 0x00008000 /* Internal ROM size (32Kb) */ 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #define ATMEL_BASE_UHP 0x00500000 /* USB Host controller */ 106*4882a593Smuzhiyun #define ATMEL_BASE_LCDC 0x00600000 /* LDC controller */ 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun /* 109*4882a593Smuzhiyun * External memory 110*4882a593Smuzhiyun */ 111*4882a593Smuzhiyun #define ATMEL_BASE_CS0 0x10000000 /* typically NOR */ 112*4882a593Smuzhiyun #define ATMEL_BASE_CS1 0x20000000 /* SDRAM */ 113*4882a593Smuzhiyun #define ATMEL_BASE_CS2 0x30000000 114*4882a593Smuzhiyun #define ATMEL_BASE_CS3 0x40000000 /* typically NAND */ 115*4882a593Smuzhiyun #define ATMEL_BASE_CS4 0x50000000 116*4882a593Smuzhiyun #define ATMEL_BASE_CS5 0x60000000 117*4882a593Smuzhiyun #define ATMEL_BASE_CS6 0x70000000 118*4882a593Smuzhiyun #define ATMEL_BASE_CS7 0x80000000 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun /* Timer */ 121*4882a593Smuzhiyun #define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun /* 124*4882a593Smuzhiyun * Other misc defines 125*4882a593Smuzhiyun */ 126*4882a593Smuzhiyun #define ATMEL_PIO_PORTS 3 /* theese SoCs have 3 PIO */ 127*4882a593Smuzhiyun #define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP 128*4882a593Smuzhiyun #define ATMEL_BASE_PIO ATMEL_BASE_PIOA 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun /* 131*4882a593Smuzhiyun * SoC specific defines 132*4882a593Smuzhiyun */ 133*4882a593Smuzhiyun #if defined(CONFIG_AT91SAM9261) 134*4882a593Smuzhiyun # define ATMEL_CPU_NAME "AT91SAM9261" 135*4882a593Smuzhiyun #elif defined(CONFIG_AT91SAM9G10) 136*4882a593Smuzhiyun # define ATMEL_CPU_NAME "AT91SAM9G10" 137*4882a593Smuzhiyun #endif 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun #endif 140